Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design - researchr publication

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R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh. Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. In 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA. pages 27-32, IEEE, 2009. [doi]

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