Area and performance optimization of a generic network-on-chip architecture

Mário P. Véstias, Horácio C. Neto. Area and performance optimization of a generic network-on-chip architecture. In Claudionor José Nunes Coelho Jr., Ricardo P. Jacobi, Jürgen Becker, editors, Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006. pages 68-73, ACM, 2006. [doi]

Abstract

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