A 65nm 1Gb 2b/Cell NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR interface

Corrado Villa, Daniele Vimercati, Stefan Schippers, Salvatore Polizzi, Andrea Scavuzzo, Maurizio Perroni, Maurizio Gaibotti, Mauro Luigi Sali. A 65nm 1Gb 2b/Cell NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR interface. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 476-616, IEEE, 2007. [doi]

@inproceedings{VillaVSPSPGS07,
  title = {A 65nm 1Gb 2b/Cell NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR interface},
  author = {Corrado Villa and Daniele Vimercati and Stefan Schippers and Salvatore Polizzi and Andrea Scavuzzo and Maurizio Perroni and Maurizio Gaibotti and Mauro Luigi Sali},
  year = {2007},
  doi = {10.1109/ISSCC.2007.373501},
  url = {http://dx.doi.org/10.1109/ISSCC.2007.373501},
  researchr = {https://researchr.org/publication/VillaVSPSPGS07},
  cites = {0},
  citedby = {0},
  pages = {476-616},
  booktitle = {2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007},
  publisher = {IEEE},
  isbn = {1-4244-0853-9},
}