A technique for minimizing power during FPGA placement

Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-chung Hsu, Arun Kundu, Andrew A. Kennings. A technique for minimizing power during FPGA placement. In FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008. pages 233-238, IEEE, 2008. [doi]

Abstract

Abstract is missing.