Gate Stack Resistance and Limits to CMOS Logic Performance

Richard A. Wachnik, Sungjae Lee, Li-Hong Pan, Hongmei Li, Ning Lu, Jing Wang, Christophe Bernicot, Raphael Bingert, Mai Randall, Scott K. Springer, Christopher S. Putnam. Gate Stack Resistance and Limits to CMOS Logic Performance. IEEE Trans. on Circuits and Systems, 61-I(8):2318-2325, 2014. [doi]

Abstract

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