33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models - researchr publication authors

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Weier Wan, Rajkumar Kubendran, Sukru Burc Eryilmaz, Wenqiang Zhang, Yan Liao, Dabin Wu, Stephen R. Deiss, Bin Gao 0006, Priyanka Raina, Siddharth Joshi, Huaqiang Wu, Gert Cauwenberghs, H.-S. Philip Wong. 33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. In 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020. pages 498-500, IEEE, 2020. [doi]

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