Weier Wan, Rajkumar Kubendran, Sukru Burc Eryilmaz, Wenqiang Zhang, Yan Liao, Dabin Wu, Stephen R. Deiss, Bin Gao 0006, Priyanka Raina, Siddharth Joshi, Huaqiang Wu, Gert Cauwenberghs, H.-S. Philip Wong. 33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. In 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020. pages 498-500, IEEE, 2020. [doi]
@inproceedings{WanKEZLWD0RJWCW20,
title = {33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models},
author = {Weier Wan and Rajkumar Kubendran and Sukru Burc Eryilmaz and Wenqiang Zhang and Yan Liao and Dabin Wu and Stephen R. Deiss and Bin Gao 0006 and Priyanka Raina and Siddharth Joshi and Huaqiang Wu and Gert Cauwenberghs and H.-S. Philip Wong},
year = {2020},
doi = {10.1109/ISSCC19947.2020.9062979},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062979},
researchr = {https://researchr.org/publication/WanKEZLWD0RJWCW20},
cites = {0},
citedby = {0},
pages = {498-500},
booktitle = {2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020},
publisher = {IEEE},
isbn = {978-1-7281-3205-1},
}