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A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications

Y. Wang, H. Ahn, Uddalak Bhattacharya, T. Coan, Fatih Hamzaoglu, W. Hafez, C.-H. Jan, R. Kolar, S. Kulkarni, J. Lin, Y. Ng, I. Post, L. Wel, Y. Zhang, K. Zhang, Mark Bohr. A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 324-606, IEEE, 2007. [doi]

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Y. Wang

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H. Ahn

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Uddalak Bhattacharya

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T. Coan

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Fatih Hamzaoglu

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W. Hafez

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C.-H. Jan

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R. Kolar

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S. Kulkarni

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J. Lin

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Y. Ng

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I. Post

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L. Wel

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Y. Zhang

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K. Zhang

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Mark Bohr

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