A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique - researchr publication authors

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Lin Wang, Yong Chen 0005, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. IEEE Trans. Circuits Syst. I Regul. Pap., 70(7):2637-2650, July 2023. [doi]

This author has not been identified. Look up 'Lin Wang' in GoogleThis author has not been identified. Look up 'Yong Chen 0005' in GoogleThis author has not been identified. Look up 'Chaowei Yang' in GoogleThis author has not been identified. Look up 'Xiaoteng Zhao' in GoogleThis author has not been identified. Look up 'Pui-In Mak' in GoogleThis author has not been identified. Look up 'Franco Maloberti' in GoogleThis author has not been identified. Look up 'Rui Paulo Martins' in Google

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