A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique

Lin Wang, Yong Chen 0005, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. IEEE Trans. Circuits Syst. I Regul. Pap., 70(7):2637-2650, July 2023. [doi]

Abstract

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