Tile/line access cache memory based on a multi-level Z-order tiling data layout

Baokang Wang, Yuki Fukazawa, Toshio Kondo, Takahiro Sasaki. Tile/line access cache memory based on a multi-level Z-order tiling data layout. Concurrency - Practice and Experience, 30(9), 2018. [doi]

Abstract

Abstract is missing.