A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng. A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. IEEE Trans. VLSI Syst., 16(5):594-598, 2008. [doi]

Abstract

Abstract is missing.