Xiaoyang Wang, Qiang Li. A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS. In IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014. pages 309-312, IEEE, 2014. [doi]
@inproceedings{WangL14-28,
title = {A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS},
author = {Xiaoyang Wang and Qiang Li},
year = {2014},
doi = {10.1109/ISCAS.2014.6865127},
url = {http://dx.doi.org/10.1109/ISCAS.2014.6865127},
researchr = {https://researchr.org/publication/WangL14-28},
cites = {0},
citedby = {0},
pages = {309-312},
booktitle = {IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014},
publisher = {IEEE},
}