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Mingyu Wang, Zhaolin Li. An area- and energy-efficient hybrid architecture for floating-point FFT computations. Microprocessors and Microsystems, 65:14-22, 2019. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A hybrid SDC/SDF architecture for area and power minimization of floating-point FFT computationsMingyu Wang, Zhaolin Li. iscas 2016: 2170-2173 [doi] A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computationsMingyu Wang, Fang Wang, Shaojun Wei, Zhaolin Li. mj, 47:19-30, 2016. [doi]
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