Tzu-Han Wang, Chenyang Li, Dong Suk Kang, Ken Li, Xitie Zhang, Wei-En Lee, Visvesh Sathe 0001, Shaolan Li. A 50-kHz BW 92.1-dB SNDR Incremental ADC Using a Back-End Sampling Two-Step NS-SAR Architecture with Concurrent Gain-Error + Noise Suppression. In IEEE Custom Integrated Circuits Conference, CICC 2025, Boston, MA, USA, April 13-17, 2025. pages 1-3, IEEE, 2025. [doi]
Abstract is missing.