The following publications are possibly variants of this publication:
- Effects of different drop test conditions on board-level reliability of chip-scale packagesYi-Shao Lai, Po-Chuan Yang, Chang-Lin Yeh. mr, 48(2):274-281, 2008. [doi]
- Evaluation of board-level reliability of electronic packages under consecutive dropsChang-Lin Yeh, Yi-Shao Lai, Chin-Li Kao. mr, 46(7):1172-1182, 2006. [doi]
- Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test conditionYi-Shao Lai, Ping-Feng Yang, Chang-Lin Yeh. mr, 46(2-4):645-650, 2006. [doi]
- Cyclic bending reliability of wafer-level chip-scale packagesYi-Shao Lai, Tong Hong Wang, Han-Hui Tsai, Ming-Hwa R. Jen. mr, 47(1):111-117, 2007. [doi]