Yi-Shao Lai - researchr alias

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Viewing Publication 1 - 55 from 55

2015

Thermal resistance of side by side multi-chip package: Thermal mode analysisDao-Long Chen, Tei-Chen Chen, Ping-Feng Yang, Yi-Shao Lai. mr, 55(5):822-831, 2015. [doi]

Power electronics packagingKatsuaki Suganuma, Jenn-Ming Song, Yi-Shao Lai. mr, 55(12):2523, 2015. [doi]

Characterising Arrhenius moisture diffusivity constants using non-isothermal sorptionE. H. Wong, J. Cook, M. Dreno, Dao-Long Chen, Yi-Shao Lai. mr, 55(11):2331-2335, 2015. [doi]

2014

Investigation of electromigration reliability of redistribution lines in wafer-level chip-scale packagesChin-Li Kao, Tei-Chen Chen, Yi-Shao Lai, Ying-Ta Chiu. mr, 54(11):2471-2478, 2014. [doi]

2/ZnO filmsWun-Kai Wang, Hua-Chiang Wen, Chun-Hu Cheng, Ching-Hua Hung, Wu-Ching Chou, Wei-Hung Yau, Ping-Feng Yang, Yi-Shao Lai. mr, 54(12):2754-2759, 2014. [doi]

2013

Reliability of micro-interconnects in 3D IC packagesC. Robert Kao, Albert T. Wu, King-Ning Tu, Yi-Shao Lai. mr, 53(1):1, 2013. [doi]

Study of factors affecting warpage of HFCBGA subjected to reflow soldering-liked profileTong Hong Wang, Ching-I. Tsai, Chang-Chi Lee, Yi-Shao Lai. mr, 53(2):297-302, 2013. [doi]

2012

A review of three-dimensional viscoelastic models with an application to viscoelasticity characterization using nanoindentationDao-Long Chen, Ping-Feng Yang, Yi-Shao Lai. mr, 52(3):541-558, 2012. [doi]

The performance and fracture mechanism of solder joints under mechanical reliability testWei-Luen Jang, Tai-Siang Wang, Yen-Fen Lai, Kwang-Lung Lin, Yi-Shao Lai. mr, 52(7):1428-1434, 2012. [doi]

Structural design guideline to minimize extreme low-k delamination potential in 40 nm flip-chip packagesYi-Shao Lai, Meng-Kai Shih, Chang-Chi Lee, Tong Hong Wang. mr, 52(11):2851-2855, 2012. [doi]

Reliability of high-power LED packaging and assemblyCheng-Yi Liu, S. W. Ricky Lee, Moo Whan Shin, Yi-Shao Lai. mr, 52(5):761, 2012. [doi]

Influence of trace alloying elements on the ball impact test reliability of SnAgCu solder jointsJenn-Ming Song, Yao-Ren Liu, Yi-Shao Lai, Ying-Ta Chiu, Ning-Cheng Lee. mr, 52(1):180-189, 2012. [doi]

Guest Editorial - Low Temperature Processing for Microelectronics and Microsystems PackagingTadatomo Suga, Jenn-Ming Song, Yi-Shao Lai. mr, 52(2):301, 2012. [doi]

2011

Fine pitch copper wire bonding in high volume productionBernd K. Appelt, Andy Tseng, Chun-Hsiung Chen, Yi-Shao Lai. mr, 51(1):13-20, 2011. [doi]

Investigation of growth behavior of Al-Cu intermetallic compounds in Cu wire bondingJiunn Chen, Yi-Shao Lai, Yi-Wun Wang, C. R. Kao. mr, 51(1):125-129, 2011. [doi]

Warpage evolution of overmolded ball grid array package during post-mold curing thermal processTz-Cheng Chiu, Hong-Wei Huang, Yi-Shao Lai. mr, 51(12):2263-2273, 2011. [doi]

Characteristic of copper wire and transient analysis on wirebonding processHsiang-Chen Hsu, Wei-Yao Chang, Chang-Lin Yeh, Yi-Shao Lai. mr, 51(1):179-186, 2011. [doi]

Copper Wire BondingMichael Mayer, Yi-Shao Lai. mr, 51(1):1-2, 2011. [doi]

Determination of residual strains of the EMC in PBGA during manufacturing and IR solder reflow processesM.-Y. Tsai, C. W. Ting, C.-Y. Huang, Yi-Shao Lai. mr, 51(3):642-648, 2011. [doi]

Effect of surface roughness of silicon die and copper heat spreader on thermal performance of HFCBGATong Hong Wang, Sara N. Paisner, Chang-Chi Lee, Susan Chen, Yi-Shao Lai. mr, 51(8):1372-1376, 2011. [doi]

0.2/Si filmsMing-Jhang Wu, Hua-Chiang Wen, Shyh-Chi Wu, Ping-Feng Yang, Yi-Shao Lai, Wen-Kuang Hsu, Wen-Fa Wu, Chang-Pin Chou. mr, 51(12):2223-2227, 2011. [doi]

2010

Geometric design for ultra-long needle probe card for digital light processing wafer testingHao-Yuan Chang, Wen-Fung Pan, Meng-Kai Shih, Yi-Shao Lai. mr, 50(4):556-563, 2010. [doi]

Redistribution in wafer level chip size packaging technology for high power device applications: Process and design considerationsJiunn Chen, Yi-Shao Lai, Chueh-An Hsieh, Chia Yi Hu. mr, 50(4):522-527, 2010. [doi]

Evaluation of the nanoindentation behaviors of SiGe epitaxial layer on Si substrateBo-Ching He, Chun-Hu Cheng, Hua-Chiang Wen, Yi-Shao Lai, Ping-Feng Yang, Meng-Hung Lin, Wen-Fa Wu, Chang-Pin Chou. mr, 50(1):63-69, 2010. [doi]

Effect of annealing treatment and nanomechanical properties for multilayer Si::0.8::Ge::0.2::-Si filmsBo-Ching He, Hua-Chiang Wen, Meng-Hung Lin, Yi-Shao Lai, Wen-Fa Wu, Chang-Pin Chou. mr, 50(6):851-856, 2010. [doi]

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip packageTheresa Sze, Darko Popovic, Jing Shi, Yi-Shao Lai, James G. Mitchell, Bruce Guenin, Tsung-Yueh Tsai, Chin-Li Kao, Matthew Giere. mr, 50(4):498-506, 2010. [doi]

Advances in Wafer Level Packaging (WLP)Tong Yan Tee, Xuejun Fan, Yi-Shao Lai. mr, 50(4):479-480, 2010. [doi]

2009

2008

Effects of different drop test conditions on board-level reliability of chip-scale packagesYi-Shao Lai, Po-Chuan Yang, Chang-Lin Yeh. mr, 48(2):274-281, 2008. [doi]

Finite element model verification for packaged printed circuit board by experimental modal analysisYing-Chih Lee, Bor-Tsuen Wang, Yi-Shao Lai, Chang-Lin Yeh, Rong-Sheng Chen. mr, 48(11-12):1837-1846, 2008. [doi]

Structural design optimization for board-level drop reliability of wafer-level chip-scale packagesTsung-Yueh Tsai, Yi-Shao Lai, Chang-Lin Yeh, Rong-Sheng Chen. mr, 48(5):757-762, 2008. [doi]

Reliability evaluations for board-level chip-scale packages under coupled power and thermal cycling test conditionsTong Hong Wang, Yi-Shao Lai, Yu-Cheng Lin. mr, 48(1):132-139, 2008. [doi]

Characteristics of ZnO thin films prepared by radio frequency magnetron sputteringPing-Feng Yang, Hua-Chiang Wen, Sheng-Rui Jian, Yi-Shao Lai, Sean Wu, Rong-Sheng Chen. mr, 48(3):389-394, 2008. [doi]

Investigations of solder joint damage potentials for board-level chip-scale packages subjected to consecutive dropsChang-Lin Yeh, Yi-Shao Lai. mr, 48(2):282-292, 2008. [doi]

2007

Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packagesYi-Shao Lai, Tong Hong Wang. mr, 47(1):104-110, 2007. [doi]

Electromigration of Sn-37Pb and Sn-3Ag-1.5Cu/Sn-3Ag-0.5Cu composite flip-chip solder bumps with Ti/Ni(V)/Cu under bump metallurgyYi-Shao Lai, Kuo-Ming Chen, Chin-Li Kao, Chiu-Wen Lee, Ying-Ta Chiu. mr, 47(8):1273-1279, 2007. [doi]

Evaluation of solder joint strengths under ball impact testYi-Shao Lai, Hsiao-Chuan Chang, Chang-Lin Yeh. mr, 47(12):2179-2187, 2007. [doi]

Cyclic bending reliability of wafer-level chip-scale packagesYi-Shao Lai, Tong Hong Wang, Han-Hui Tsai, Ming-Hwa R. Jen. mr, 47(1):111-117, 2007. [doi]

Response spectra analysis for undamped structural systems subjected to half-sine impact acceleration pulsesTsung-Yueh Tsai, Chang-Lin Yeh, Yi-Shao Lai, Rong-Sheng Chen. mr, 47(8):1239-1245, 2007. [doi]

Empirical correlation between package-level ball impact test and board-level drop reliabilityChang-Lin Yeh, Yi-Shao Lai, Hsiao-Chuan Chang, Tsan-Hsien Chen. mr, 47(7):1127-1134, 2007. [doi]

Transient analysis of drop responses of board-level electronic packages using response spectra incorporated with modal superpositionChang-Lin Yeh, Tsung-Yueh Tsai, Yi-Shao Lai. mr, 47(12):2188-2196, 2007. [doi]

2006

On solution schemes for time-independent thermomechanical analysis for structures containing polymeric materialsYi-Shao Lai. mr, 46(5-6):859-863, 2006. [doi]

Electrothermal coupling analysis of current crowding and Joule heating in flip-chip packagesYi-Shao Lai, Chin-Li Kao. mr, 46(8):1357-1368, 2006. [doi]

Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test conditionYi-Shao Lai, Ping-Feng Yang, Chang-Lin Yeh. mr, 46(2-4):645-650, 2006. [doi]

Characteristics of current crowding in flip-chip solder bumpsYi-Shao Lai, Chin-Li Kao. mr, 46(5-6):915-922, 2006. [doi]

Transient fracturing of solder joints subjected to displacement-controlled impact loadsChang-Lin Yeh, Yi-Shao Lai. mr, 46(5-6):885-895, 2006. [doi]

Support excitation scheme for transient analysis of JEDEC board-level drop testChang-Lin Yeh, Yi-Shao Lai. mr, 46(2-4):626-636, 2006. [doi]

Evaluation of board-level reliability of electronic packages under consecutive dropsChang-Lin Yeh, Yi-Shao Lai, Chin-Li Kao. mr, 46(7):1172-1182, 2006. [doi]

2005

Verification of submodeling technique in thermomechanical reliability assessment of flip-chip package assemblyYi-Shao Lai, Tong Hong Wang. mr, 45(3-4):575-582, 2005. [doi]

Transient analysis of the impact stage of wirebonding on Cu/low-K wafersChang-Lin Yeh, Yi-Shao Lai. mr, 45(2):371-378, 2005. [doi]

1993

An Observation on Fractal Characteristics of Individual River Plan FormsRay-Shyan Wu, Yi-Shao Lai. fractals 1994: 441-451

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2015

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1993

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