Zhehong Wang, Ziyun Li, Li Xu, Qing Dong 0001, Chin-I Su, Wen-Ting Chu, George Tsou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw. An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM. In IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020. pages 1-2, IEEE, 2020. [doi]
@inproceedings{WangLX0SCTCCSKB20,
title = {An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM},
author = {Zhehong Wang and Ziyun Li and Li Xu and Qing Dong 0001 and Chin-I Su and Wen-Ting Chu and George Tsou and Yu-Der Chih and Tsung-Yung Jonathan Chang and Dennis Sylvester and Hun-Seok Kim and David T. Blaauw},
year = {2020},
doi = {10.1109/VLSICircuits18222.2020.9162811},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162811},
researchr = {https://researchr.org/publication/WangLX0SCTCCSKB20},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020},
publisher = {IEEE},
isbn = {978-1-7281-9942-9},
}