Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang. Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture. In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016. pages 5, ACM, 2016. [doi]
@inproceedings{WangLY16-6,
title = {Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture},
author = {Po-Han Wang and Cheng-Hsuan Li and Chia-Lin Yang},
year = {2016},
doi = {10.1145/2897937.2898036},
url = {http://doi.acm.org/10.1145/2897937.2898036},
researchr = {https://researchr.org/publication/WangLY16-6},
cites = {0},
citedby = {0},
pages = {5},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016},
publisher = {ACM},
isbn = {978-1-4503-4236-0},
}