Yifan Wang, Chhandak Mukherjee, Houssem Rezgui, Marina Deng, Cristell Maneux, Sara Mannaa, Ian O'Connor, Jonas Müller, Sylvain Pelloquin, Guilhem Larrieu. Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design. In 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023, Lisbon, Portugal, September 11-14, 2023. pages 57-60, IEEE, 2023. [doi]
Abstract is missing.