Wei Wang, Vasilis F. Pavlidis, Yuanqing Cheng. Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength. In Tinoosh Mohsenin, Weisheng Zhao, Yiran Chen, Onur Mutlu, editors, GLSVLSI '20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020. pages 399-404, ACM, 2020. [doi]
Abstract is missing.