Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li. Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. In 32nd IEEE International Conference on Computer Design, ICCD 2014, Seoul, South Korea, October 19-22, 2014. pages 133-138, IEEE, 2014. [doi]
@inproceedings{WangRWBL14,
title = {Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration},
author = {Jianxing Wang and Pooja Roy and Weng-Fai Wong and Xiuyuan Bi and Hai Li},
year = {2014},
doi = {10.1109/ICCD.2014.6974672},
url = {http://dx.doi.org/10.1109/ICCD.2014.6974672},
researchr = {https://researchr.org/publication/WangRWBL14},
cites = {0},
citedby = {0},
pages = {133-138},
booktitle = {32nd IEEE International Conference on Computer Design, ICCD 2014, Seoul, South Korea, October 19-22, 2014},
publisher = {IEEE},
isbn = {978-1-4799-6492-5},
}