A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology - researchr publication authors

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Chua-Chin Wang, Tsung-Yi Tsai, Wei Lin. A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology. In 2015 International Conference on IC Design & Technology, ICICDT 2015, Leuven, Belgium, June 1-3, 2015. pages 1-4, IEEE, 2015. [doi]

This author has not been identified. Look up 'Chua-Chin Wang' in GoogleThis author has not been identified. Look up 'Tsung-Yi Tsai' in GoogleThis author has not been identified. Look up 'Wei Lin' in Google

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