The following publications are possibly variants of this publication:
- A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technologyChua-Chin Wang, Wen-Je Lu, Hsin-Yuan Tseng. iscas 2013: 2079-2082 [doi]
- Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technologyChua-Chin Wang, Wen-Je Lu, Kai-Wei Juan, Wei Lin, Hsin-Yuan Tseng, Chun-Ying Juan. mj, 46(1):1-11, 2015. [doi]
- 2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage CompensationChua-Chin Wang, Zong-You Hou, Kai-Wei Ruan. tcas, 64(7):812-816, 2017. [doi]
- 32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensationTzung-Je Lee, Kai-Wei Ruan, Chua-Chin Wang. icicdt 2014: 1-4 [doi]
- 40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew RateChua-Chin Wang, Zong-You Hou, Ssu-Wei Huang. apccas 2018: 279-282 [doi]
- A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and aboveTsung-Yi Tsai, Yan-You Chou, Chua-Chin Wang. icicdt 2016: 1-4 [doi]
- Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL VariationsChua-Chin Wang. tcasII, 68(2):562-567, 2021. [doi]
- 500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage VariationsChua-Chin Wang, Tsung-Yi Tsai, Yu-Lin Deng, Tzung-Je Lee. cssp, 38(2):556-568, 2019. [doi]
- 2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage VariationsChua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang. jcsc, 29(6), 2020. [doi]
- 2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS ProcessChua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Yan-You Chou, Tzung-Je Lee. cssp, 40(6):2824-2840, 2021. [doi]