Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Guohui Wang, Aida Vosoughi, Hao Shen, Joseph R. Cavallaro, Yuanbin Guo. Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013. pages 1340-1343, IEEE, 2013. [doi]

Abstract

Abstract is missing.