A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations

Mingyu Wang, Fang Wang, Shaojun Wei, Zhaolin Li. A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations. Microelectronics Journal, 47:19-30, 2016. [doi]

Authors

Mingyu Wang

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Fang Wang

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Shaojun Wei

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Zhaolin Li

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