Mingyu Wang, Fang Wang, Shaojun Wei, Zhaolin Li. A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations. Microelectronics Journal, 47:19-30, 2016. [doi]
@article{WangWWL16,
title = {A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations},
author = {Mingyu Wang and Fang Wang and Shaojun Wei and Zhaolin Li},
year = {2016},
doi = {10.1016/j.mejo.2015.11.004},
url = {http://dx.doi.org/10.1016/j.mejo.2015.11.004},
researchr = {https://researchr.org/publication/WangWWL16},
cites = {0},
citedby = {0},
journal = {Microelectronics Journal},
volume = {47},
pages = {19-30},
}