Huanyu Wang, Geng Xie, Jie Gu. Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design. In Proceedings of the 2016 International Symposium on Low Power Electronics and Design, ISLPED 2016, San Francisco Airport, CA, USA, August 08 - 10, 2016. pages 22-27, ACM, 2016. [doi]
@inproceedings{WangXG16,
title = {Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design},
author = {Huanyu Wang and Geng Xie and Jie Gu},
year = {2016},
doi = {10.1145/2934583.2934584},
url = {http://doi.acm.org/10.1145/2934583.2934584},
researchr = {https://researchr.org/publication/WangXG16},
cites = {0},
citedby = {0},
pages = {22-27},
booktitle = {Proceedings of the 2016 International Symposium on Low Power Electronics and Design, ISLPED 2016, San Francisco Airport, CA, USA, August 08 - 10, 2016},
publisher = {ACM},
isbn = {978-1-4503-4185-1},
}