The following publications are possibly variants of this publication:
- A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash MemoryYi Wang, Zili Shao, Henry C. B. Chan, Luis Angel D. Bathen, Nikil D. Dutt. tvlsi, 22(11):2402-2410, 2014. [doi]
- 2-gate-dielectric select gates in vertical-channel three-dimensional (3D) NAND flash memoryBo Wang, Bin Gao, Huaqiang Wu, He Qian. mr, 78:80-84, 2017. [doi]