Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier - researchr publication related

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Jinn-Shyan Wang, Po-Hui Yang. Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier. In Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan. pages 225-228, ACM, 2000. [doi]

The following publications are possibly variants of this publication:

Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flopsJinn-Shyan Wang, Po-Hui Yang, Duo Sheng. jssc, 35(4):583-592, 2000. [doi]

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