A high-resolution pipeline time-to-digital converter in 0.18μm CMOS technology

Yongsheng Wang, Qiao Ye, Han Zhao, Xiaowei Liu. A high-resolution pipeline time-to-digital converter in 0.18μm CMOS technology. In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 624-627, IEEE, 2017. [doi]

Abstract

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