An all digital delay lock loop architecture for high precision timing generator - researchr publication authors

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Mohammad Waris, Urvi Mehta, Rajiv Kumaran, Sanjeev Mehta, Arup Roy Chowdhury. An all digital delay lock loop architecture for high precision timing generator. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. pages 1-6, IEEE, 2015. [doi]

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