Mohammad Waris, Urvi Mehta, Rajiv Kumaran, Sanjeev Mehta, Arup Roy Chowdhury. An all digital delay lock loop architecture for high precision timing generator. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. pages 1-6, IEEE, 2015. [doi]
@inproceedings{WarisMKMC15,
title = {An all digital delay lock loop architecture for high precision timing generator},
author = {Mohammad Waris and Urvi Mehta and Rajiv Kumaran and Sanjeev Mehta and Arup Roy Chowdhury},
year = {2015},
doi = {10.1109/ISVDAT.2015.7208138},
url = {http://dx.doi.org/10.1109/ISVDAT.2015.7208138},
researchr = {https://researchr.org/publication/WarisMKMC15},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015},
publisher = {IEEE},
isbn = {978-1-4799-1743-3},
}