An Implementation of a World Grid Square Codes Generator on a RISC-V Processor

Rei Watanabe, Jubee Tada, Keiichi Sato. An Implementation of a World Grid Square Codes Generator on a RISC-V Processor. In Ninth International Symposium on Computing and Networking, CANDAR 2021 - Workshops, Matsue, Japan, 23-26 November 2021. pages 309-312, IEEE, 2021. [doi]

@inproceedings{WatanabeTS21,
  title = {An Implementation of a World Grid Square Codes Generator on a RISC-V Processor},
  author = {Rei Watanabe and Jubee Tada and Keiichi Sato},
  year = {2021},
  doi = {10.1109/CANDARW53999.2021.00059},
  url = {https://doi.org/10.1109/CANDARW53999.2021.00059},
  researchr = {https://researchr.org/publication/WatanabeTS21},
  cites = {0},
  citedby = {0},
  pages = {309-312},
  booktitle = {Ninth International Symposium on Computing and Networking, CANDAR 2021 - Workshops, Matsue, Japan, 23-26 November 2021},
  publisher = {IEEE},
  isbn = {978-1-6654-2835-4},
}