Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI - researchr publication authors

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Takahiro Watanabe, Minoru Watanabe. Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI. In 55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012. pages 117-120, IEEE, 2012. [doi]

This author has not been identified. Look up 'Takahiro Watanabe' in GoogleThis author has not been identified. Look up 'Minoru Watanabe' in Google

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