Takahiro Watanabe, Minoru Watanabe. Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI. In 55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012. pages 117-120, IEEE, 2012. [doi]
@inproceedings{WatanabeW12-3,
title = {Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI},
author = {Takahiro Watanabe and Minoru Watanabe},
year = {2012},
doi = {10.1109/MWSCAS.2012.6291971},
url = {https://doi.org/10.1109/MWSCAS.2012.6291971},
researchr = {https://researchr.org/publication/WatanabeW12-3},
cites = {0},
citedby = {0},
pages = {117-120},
booktitle = {55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012},
publisher = {IEEE},
isbn = {978-1-4673-2526-4},
}