The following publications are possibly variants of this publication:
- An optically differential reconfigurable gate array using a 0.18 μm CMOS processMinoru Watanabe, Fuminori Kobayashi. socc 2004: 281-284 [doi]
- Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSIShinichi Kato, Minoru Watanabe. samos 2009: 139-148 [doi]
- Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSIShinichi Kato, Minoru Watanabe. fpt 2008: 377-380 [doi]
- An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration CircuitMinoru Watanabe, Fuminori Kobayashi. ipps 2005: [doi]
- 0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSITakahiro Watanabe, Minoru Watanabe. isvlsi 2012: 308-313 [doi]
- Enhanced Radiation Tolerance of an Optically Reconfigurable Gate Array by Exploiting an Inversion/Non-inversion ImplementationTakashi Yoza, Minoru Watanabe. arc 2014: 156-166 [doi]
- Reconfiguration Performance Recovery on Optically Reconfigurable Gate ArraysTomoya Akabe, Minoru Watanabe. vlsid 2016: 603-604 [doi]
- A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSIM. Watanabe, F. Kobayashi. aspdac 2007: 124-125 [doi]
- A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technologyMinoru Watanabe, Fuminori Kobayashi. aspdac 2006: 108-109 [doi]