An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel

Xin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng 0001. An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019. pages 1040-1045, IEEE, 2019. [doi]

@inproceedings{WeiYZZ019,
  title = {An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel},
  author = {Xin Wei and Changhao Yan and Hai Zhou and Dian Zhou and Xuan Zeng 0001},
  year = {2019},
  doi = {10.23919/DATE.2019.8714992},
  url = {https://doi.org/10.23919/DATE.2019.8714992},
  researchr = {https://researchr.org/publication/WeiYZZ019},
  cites = {0},
  citedby = {0},
  pages = {1040-1045},
  booktitle = {Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019},
  publisher = {IEEE},
  isbn = {978-3-9819263-2-3},
}