Table of Contents

• One Fault is All it Needs: Breaking Higher-Order Masking with Persistent Fault AnalysisJingyu Pan, Fan Zhang 0010, Kui Ren, Shivam Bhasin. 1-6 [doi]
• Multi-Tenant FPGA-based Reconfigurable Systems: Attacks and DefensesRana Elnaggar, Ramesh Karri, Krishnendu Chakrabarty. 7-12 [doi]
• Spying on Temperature using DRAMWenjie Xiong 0001, Nikolaos Athanasios Anagnostopoulos, André Schaller, Stefan Katzenbeisser 0001, Jakub Szefer. 13-18 [doi]
• Mitigating Power Supply Glitch based Fault Attacks with Fast All-Digital Clock Modulation CircuitArvind Singh, Monodeep Kar, Nikhil Chawla, Saibal Mukhopadhyay. 19-24 [doi]
• Dual-gate self-aligned a-InGaZnO transistor model for flexible circuit applicationsFlorian De Roose, Hikmet Celiker, Jan Genoe, Wim Dehaene, Kris Myny. 25-29 [doi]
• Predictive Modeling and Design Automation of Inorganic Printed ElectronicsFarhan Rasheed, Michael Hefenbrock, Rajendra Bishnoi, Michael Beigl, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori. 30-35 [doi]
• Process Design Kit and Design Automation for Flexible Hybrid ElectronicsTsung-Ching Huang, Ting Lei, Leilai Shao, Sridhar Sivapurapu, Madhavan Swaminathan, Sicheng Li, Zhenan Bao, Kwang-Ting Cheng, Raymond G. Beausoleil. 36-41 [doi]
• Circuit Design and Design Automation for Printed ElectronicsM. Fattori, I. A. Fijn, L. Hu, Eugenio Cantatore, Fabrizio Torricelli, M. Charbonneau. 42-47 [doi]
• Hot Spot Identification and System Parameterized Thermal Modeling for Multi-Core Processors Through Infrared Thermal ImagingSheriff Sadiqbatcha, Hengyang Zhao, Hussam Amrouch, Jörg Henkel, Sheldon X.-D. Tan. 48-53 [doi]
• Litho-GPA: Gaussian Process Assurance for Lithography Hotspot DetectionWei Ye, Mohamed Baker Alawieh, Meng Li 0004, Yibo Lin, David Z. Pan. 54-59 [doi]
• PinT: Polynomial in Temperature Decode Weights in a Neuromorphic ArchitectureScott Reid, Antonio Montoya, Kwabena Boahen. 60-65 [doi]
• Enhancing Two-Phase Cooling Efficiency through Thermal-Aware Workload Mapping for Power-Hungry ServersArman Iranfar, Ali Pahlevan, Marina Zapater, David Atienza. 66-71 [doi]
• IR-aware Power Net Routing for Multi-Voltage Mixed-Signal DesignShuo-Hui Wang, Guan-Hong Liou, Yen-Yu Su, Mark Po-Hung Lin. 72-77 [doi]
• Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability SimulatorA. Toro-Frias, P. Saraza-Canflanca, Fábio Passos, P. Martín-Lloret, R. Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodriguez, Montserrat Nafria, Francisco V. Fernández. 78-83 [doi]
• MixLock: Securing Mixed-Signal Circuits via Logic LockingJulian Leonhard, Muhammad Yasin, Shadi Turk, Mohammed Thari Nabeel, Marie-Minerve Louërat, Roselyne Chotin-Avot, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos. 84-89 [doi]
• Matrix-Vector vs. Matrix-Matrix Multiplication: Potential in DD-based Simulation of Quantum ComputationsAlwin Zulehner, Robert Wille. 90-95 [doi]
• Automated Circuit Approximation Method Driven by Data DistributionZdenek Vasícek, Vojtech Mrazek, Lukás Sekanina. 96-101 [doi]
• Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network TransceiverPaul Detterer, Cumhur Erdin, Majid Nabi, José Pineda de Gyvez, Twan Basten, Hailong Jiao. 102-107 [doi]
• Approximate Random Dropout for DNN training acceleration in GPGPUZhuoran Song, Ru Wang, Dongyu Ru, Zhenghao Peng, Hongru Huang, Hai Zhao, Xiaoyao Liang, Li Jiang 0002. 108-113 [doi]
• Low-Complexity Dynamic Channel Scaling of Noise-Resilient CNN for Intelligent Edge DevicesYounghoon Byun, Minho Ha, Jeonghun Kim, Sunggu Lee, Youngjoo Lee. 114-119 [doi]
• Data Locality Optimization of Depthwise Separable Convolutions for CNN Inference AcceleratorsHao-Ning Wu, Chih-Tsun Huang. 120-125 [doi]
• A Binary Learning Framework for Hyperdimensional ComputingMohsen Imani, John Messerly, Fan Wu, Wang Pi, Tajana Rosing. 126-131 [doi]
• Smart Thermal Management for Heterogeneous MulticoresJörg Henkel, Heba Khdr, Martin Rapp. 132-137 [doi]
• Design and Optimization of Heterogeneous Manycore Systems Enabled by Emerging Interconnect Technologies: Promises and ChallengesBiresh Kumar Joardar, Ryan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande. 138-143 [doi]
• Power and Thermal Analysis of Commercial Mobile Platforms: Experiments and Case StudiesGanapati Bhat, Suat Gumussoy, Ümit Y. Ogras. 144-149 [doi]
• New method for the automated massive characterization of Bias Temperature Instability in CMOS transistorsP. Saraza-Canflanca, Javier Diaz-Fortuny, R. Castro-López, Elisenda Roca Moreno, Javier Martín-Martínez, Rosana Rodriguez, Montserrat Nafria, Francisco V. Fernandez. 150-155 [doi]
• Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft ErrorsKeven Feng, Sandeep Vora, Rui Jiang, Elyse Rosenbaum, Shobha Vasudevan. 156-161 [doi]
• Methodology for Application-Dependent Degradation Analysis of Memory TimingDaniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor. 162-167 [doi]
• "Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node DesignAndrew B. Kahng, Uday Mallappa, Lawrence Saul, Shangyuan Tong. 168-173 [doi]
• Dim Sum: Light Clock Tree by Small Diameter SumGengjie Chen, Evangeline F. Y. Young. 174-179 [doi]
• Routability-Driven Macro Placement with Embedded CNN-Based Prediction ModelYu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu. 180-185 [doi]
• RTL-Aware Dataflow-Driven Macro PlacementAlex Vidal-Obiols, Jordi Cortadella, Jordi Petit, Marc Galceran Oms, Ferran Martorell. 186-191 [doi]
• Realizing Reproducible and Reusable Parallel Floating Random Walk Solvers for Practical UsageMingye Song, Zhezhao Xu, Wenjian Yu, Lei Yin. 192-197 [doi]
• Optically Interrogated Unique Object with Simulation Attack PreventionPovilas Marcinkevicius, Ibrahim Ethem Bagci, Nema M. Abdelazim, Christopher S. Woodhead, Robert J. Young, Utz Roedig. 198-203 [doi]
• PUFs Deep Attacks: Enhanced modeling attacks using deep learning techniques to break the security of double arbiter PUFsMahmoud Khalafalla, Catherine H. Gebotys. 204-209 [doi]
• Desieve the Attacker: Thwarting IP Theft in Sieve-Valve-based BiochipsMohammed Shayan, Sukanta Bhattacharjee, Yong-Ak Song, Krishnendu Chakrabarty, Ramesh Karri. 210-215 [doi]
• PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D FlashJing Chen, Yi Wang, Amelie Chi Zhou, Rui Mao, Tao Li. 216-221 [doi]
• Compiler-Directed and Architecture-Independent Mitigation of Read Disturbance Errors in STT-RAMFateme S. Hosseini, Chengmo Yang. 222-227 [doi]
• A Wear Leveling Aware Memory Allocator for Both Stack and Heap Management in PCM-based Main Memory SystemsWei Li, Ziqi Shuai, Chun Jason Xue, Mengting Yuan, Qingan Li. 228-233 [doi]
• Exploiting System Dynamics for Resource-Efficient Automotive CPS DesignLeslie Maldonado, Wanli Chang, Debayan Roy, Anuradha Annaswamy, Dip Goswami, Samarjit Chakraborty. 234-239 [doi]
• Implementation-aware design of image-based control with on-line measurable variable-delayRóbinson Medina Sánchez, Sander Stuijk, Dip Goswami, Twan Basten. 240-245 [doi]
• Optimizing Assume-Guarantee Contracts for Cyber-Physical System DesignChanwook Oh, Eunsuk Kang, Shinichi Shiraishi, Pierluigi Nuzzo. 246-251 [doi]
• Fault Injection on Hidden Registers in a RISC-V Rocket Processor and Software CountermeasuresJohan Laurent, Vincent Beroulle, Christophe Deleuze, Florian Pebay-Peyroula. 252-255 [doi]
• Methodology for EM Fault Injection: Charge-based Fault ModelHaohao Liao, Catherine H. Gebotys. 256-259 [doi]
• Securing Cryptographic Circuits by Exploiting Implementation Diversity and Partial Reconfiguration on FPGAsBenjamin Hettwer, Johannes Petersen, Stefan Gehrer, Heike Neumann, Tim Güneysu. 260-263 [doi]
• STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJBen Perach, Shahar Kvatinsky. 264-267 [doi]
• Adaptive Transient Leakage-Aware Linearised Model for Thermal Analysis of 3-D ICsChao Zhang, Milan Mihajlovic, Vasilis F. Pavlidis. 268-271 [doi]
• FastCool: Leakage Aware Dynamic Thermal Management of 3D MemoriesLokesh Siddhu, Preeti Ranjan Panda. 272-275 [doi]
• On the use of causal feature selection in the context of machine-learning indirect testManuel J. Barragan, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Sylvain Bourdel, S. Mir. 276-279 [doi]
• Accuracy and Compactness in Decision Diagrams for Quantum ComputationAlwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille. 280-283 [doi]
• One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate ComputingSaman Fröhlich, Daniel Große, Rolf Drechsler. 284-287 [doi]
• Reversible Pebbling Game for Quantum Memory ManagementGiulia Meuli, Mathias Soeken, Martin Roetteler, Nikolaj Bjørner, Giovanni De Micheli. 288-291 [doi]
• TypeCNN: CNN Development Framework With Flexible Data TypesPetr Rek, Lukás Sekanina. 292-295 [doi]
• Guaranteed Compression Rate for Activations in CNNs using a Frequency Pruning ApproachSebastian Vogel, Christoph Schorn, Andre Guntoro, Gerd Ascheid. 296-299 [doi]
• Runtime Monitoring Neuron Activation PatternsChih-Hong Cheng, Georg Nührenberg, Hirotoshi Yasuoka. 300-303 [doi]
• Chip Health Tracking Using Dynamic In-Situ Delay MonitoringHadi Ahmadi Balef, Kees Goossens, José Pineda de Gyvez. 304-307 [doi]
• PCFI: Program Counter Guided Fault Injection for Accelerating GPU Reliability AssessmentFritz G. Previlon, Charu Kalra, Devesh Tiwari, David R. Kaeli. 308-311 [doi]
• Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND FlashWeihua Liu, Fei Wu 0005, Meng Zhang, Yifei Wang, Zhonghai Lu, Xiangfeng Lu, Changsheng Xie. 312-315 [doi]
• Hidden-Delay-Fault Sensor for Test, Reliability and SecurityGiorgio Di Natale, Elena Ioana Vatajelu, Kalpana Senthamarai Kannan, Lorena Anghel. 316-319 [doi]
• Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar ArrayWooseok Yi, Yulhwa Kim, Jae-Joon Kim. 320-323 [doi]
• Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine LearningDaijoon Hyun, Yuepeng Fan, Youngsoo Shin. 324-327 [doi]
• *Yi-Cheng Zhao, Yu-Chieh Lin, Ting-Chi Wang, Ting-Hsiung Wang, Yun-Ru Wu, Hsin-Chang Lin, Shu-Yi Kao. 328-331 [doi]
• Aggressive Memory Speculation in HW/SW Co-Designed MachinesSimon Rokicki, Erven Rohou, Steven Derrien. 332-335 [doi]
• Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAsSatyajit Das, Kevin J. M. Martin, Philippe Coussy. 336-341 [doi]
• Thermal-Aware Design and Flow for FPGA Performance ImprovementBehnam Khaleghi, Tajana Simunic Rosing. 342-347 [doi]
• FIXER: Flow Integrity Extensions for Embedded RISC-VAsmit De, Aditya Basu, Swaroop Ghosh, Trent Jaeger. 348-353 [doi]
• Automated Activation of Multiple Targets in RTL Models using Concolic TestingYangdi Lyu, Alif Ahmed, Prabhat Mishra. 354-359 [doi]
• *Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler. 360-365 [doi]
• Data Flow Testing for SystemC-AMS Timed Data Flow ModelsMuhammad Hassan, Daniel Große, Hoang M. Le, Rolf Drechsler. 366-371 [doi]
• SAID: A Supergate-Aided Logic Synthesis Flow for Memristive CrossbarsValerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera. 372-377 [doi]
• GraphS: A Graph Processing Accelerator Leveraging SOT-MRAMShaahin Angizi, Jiao Sun, Wei Zhang, Deliang Fan. 378-383 [doi]
• CORN: In-Buffer Computing for Binary Neural NetworkLiang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Weisheng Zhao, Yuan Xie 0001. 384-389 [doi]
• An Energy Efficient Non-Volatile Flip-Flop based on CoMET TechnologyRobert Perricone, Zhaoxin Liang, Meghna G. Mankalale, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang, Xiaobo Sharon Hu. 390-395 [doi]
• Hardware Trojans in Emerging Non-Volatile MemoriesMohammad Nasim Imtiaz Khan, Karthikeyan Nagarajan, Swaroop Ghosh. 396-401 [doi]
• Evaluating Assertion Set Completeness to Expose Hardware Trojans and Verification BlindspotsNicole Fern, Kwang-Ting (Tim) Cheng. 402-407 [doi]
• Efficient Test Generation for Trojan Detection using Side Channel AnalysisYangdi Lyu, Prabhat Mishra. 408-413 [doi]
• A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOLAbhrajit Sengupta, Mohammed Nabeel, Johann Knechtel, Ozgur Sinanoglu. 414-419 [doi]
• Design Optimization of Frame Preemption in Real-Time Switched EthernetTaeju Park, Soheil Samii, Kang G. Shin. 420-425 [doi]
• CUBA: Chained Unanimous Byzantine Agreement for Decentralized Platoon ManagementEmanuel Regnath, Sebastian Steinhorst. 426-431 [doi]
• Decentralized Non-Neighbor Active Charge Balancing in Large Battery PacksAlexander Lamprecht, Martin Baumann, Tobias Massier, Sebastian Steinhorst. 432-437 [doi]
• TEEM: Online Thermal- and Energy-Efficiency Management on CPU-GPU MPSoCsSamuel Isuwa, Somdip Dey, Amit Kumar Singh, Klaus D. McDonald-Maier. 438-443 [doi]
• Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point AnalysisSourav Sanyal, Prabal Basu, Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty. 444-449 [doi]
• Fast and Low-Precision Learning in GPU-Accelerated Spiking Neural NetworkXueyuan She, Yun Long, Saibal Mukhopadhyay. 450-455 [doi]
• fbPDR: In-depth combination of forward and backward analysis in Property Directed ReachabilityTobias Seufert, Christoph Scholl. 456-461 [doi]
• High Coverage Concolic Equivalence CheckingPritam Roy, Sagar Chaki, Pankaj Chauhan. 462-467 [doi]
• Bosphorus: Bridging ANF and CNF SolversDavin Choo, Mate Soos, Kian Ming Adam Chai, Kuldeep S. Meel. 468-473 [doi]
• CUDA au Coq: A Framework for Machine-validating GPU Assembly ProgramsBenjamin Ferrell, Jun Duan, Kevin W. Hamlen. 474-479 [doi]
• AXIOM: A Scalable, Efficient and Reconfigurable Embedded PlatformRoberto Giorgi, Marco Procaccini, Farnam Khalili. 480-485 [doi]
• Applications of Computation-In-Memory Architectures based on Memristive DevicesSaid Hamdioui, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Abu Sebastian, Manuel Le Gallo, Sandeep Pande, Siebren Schaafsma, Francky Catthoor, Shidhartha Das, Fernando G. Redondo, Geethan Karunaratne, Abbas Rahimi, Luca Benini. 486-491 [doi]
• Chip-to-Cloud: an Autonomous and Energy Efficient Platform for Smart Vision ApplicationsAlberto Scionti, Simone Ciccia, Olivier Terzo, Giorgio Giordanengo. 492-497 [doi]
• On the Use of Hackathons to Enhance Collaboration in Large Collaborative Projects : - A Preliminary Case Study of the MegaM@Rt2 EU Project -Andrey Sadovykh, Dragos Truscan, Pierluigi Pierini, Gunnar Widforss, Adnan Ashraf, Hugo Brunelière, Pavel Smrz, Alessandra Bagnato, Wasif Afzal, Alexandra Espinosa Hortelano. 498-503 [doi]
• Realization of Four-Terminal Switching Lattices: Technology Development and Circuit ModelingSerzat Safaltin, Oguz Gencer, Muhammed Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, Mustafa Altun. 504-509 [doi]
• SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package DesignPete Ehrett, Todd M. Austin, Valeria Bertacco. 510-515 [doi]
• WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCsAditya Narayan, Yvain Thonnart, Pascal Vivet, César Fuguet Tortolero, Ayse Kivilcim Coskun. 516-521 [doi]
• REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNsBiresh Kumar Joardar, Bing Li, Janardhan Rao Doppa, Hai Li, Partha Pratim Pande, Krishnendu Chakrabarty. 522-527 [doi]
• Design Obfuscation through Selective Post-Fabrication Transistor-Level ProgrammingMustafa M. Shihab, Jingxiang Tian, Gaurav Rajavendra Reddy, Bo Hu, William Swartz, Benjamin Carrión Schäfer, Carl Sechen, Yiorgos Makris. 528-533 [doi]
• KC2: Key-Condition Crunching for Fast Sequential Circuit DeobfuscationKaveh Shamsi, Meng Li 0004, David Z. Pan, Yier Jin. 534-539 [doi]
• Piercing Logic Locking Keys through Redundancy IdentificationLeon Li, Alex Orailoglu. 540-545 [doi]
• FlexiCheck: An Adaptive Checkpointing Architecture for Energy Harvesting DevicesPriyanka Singla, Shubhankar Suman Singh, Smruti R. Sarangi. 546-551 [doi]
• Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled ClustersFlorian Glaser, Germain Haugou, Davide Rossi, Qiuting Huang, Luca Benini. 552-557 [doi]
• MAMUT: Multi-Agent Reinforcement Learning for Efficient Real-Time Multi-User Video TranscodingLuis Costero, Arman Iranfar, Marina Zapater, Francisco D. Igual, Katzalin Olcoz, David Atienza. 558-563 [doi]
• A Compiler for Automatic Selection of Suitable Processing-in-Memory InstructionsHameeza Ahmed, Paulo C. Santos, Joao P. C. Lima, Rafael Fão de Moura, Marco Antonio Zanata Alves, Antonio C. S. Beck, Luigi Carro. 564-569 [doi]
• Cache-Aware Kernel Tiling: An Approach for System-Level Performance Optimization of GPU-Based ApplicationsArian Maghazeh, Sudipta Chattopadhyay 0001, Petru Eles, Zebo Peng. 570-575 [doi]
• Data Subsetting: A Data-Centric Approach to Approximate ComputingYounghoon Kim, Swagath Venkataramani, Nitin Chandrachoodan, Anand Raghunathan. 576-581 [doi]
• TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable AccelerationMarcelo Brandalero, Muhammad Shafique 0001, Luigi Carro, Antonio Carlos Schneider Beck. 582-585 [doi]
• CADE: Configurable Approximate Divider for Energy EfficiencyMohsen Imani, Ricardo Garcia, Andrew Huang, Tajana Rosing. 586-589 [doi]
• HCFTL: A Locality-Aware Page-Level Flash Translation LayerHao Chen, Cheng Li, Yubiao Pan, Min Lyu, Yongkun Li, Yinlong Xu. 590-593 [doi]
• Model Checking is Possible to Verify Large-scale Vehicle Distributed Application SystemsHaitao Zhang, Ayang Tuo, Guoqiang Li 0001. 594-597 [doi]
• Automatic Assertion Generation from Natural Language Specifications Using Subtree AnalysisJunchen Zhao, Ian G. Harris. 598-601 [doi]
• Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided FuzzingHoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler. 602-605 [doi]
• Design Optimization for Hardware-Based Message Filters in Broadcast BusesLea Schonberger, Georg von der Bruggen, Horst Schirmeier, Jian-Jia Chen. 606-609 [doi]
• Vehicle Sequence Reordering with Cooperative Adaptive Cruise ControlTa-Wei Huang, Yun-Yun Tsai, Chung-Wei Lin, Tsung-Yi Ho. 610-613 [doi]
• Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure RatesJosef Strnadel. 614-617 [doi]
• Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL DesignsAman Goel, Karem A. Sakallah. 618-621 [doi]
• Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approachDimosthenis Masouros, Konstantina Koliogeorgi, Georgios Zervakis, Alexandra Kosvyra, Achilleas Chytas, Sotirios Xydis, Ioanna Chouvarda, Dimitrios Soudris. 622-625 [doi]
• Modular FPGA Acceleration of Data Analytics in Heterogenous ComputingElias Koromilas, Christoforos Kachris, Dimitrios Soudris, Francisco J. Ballesteros, Patricio Martinez, Ricardo Jiménez-Peris. 626-629 [doi]
• ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-ChipSiyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Terrence S. T. Mak. 630-633 [doi]
• Power and Performance Optimal NoC Design for CPU-GPU Architecture Using Formal ModelsLulwah Alhubail, Nader Bagherzadeh. 634-637 [doi]
• Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit RepresentationsArash Fayyazi, Soheil Shababi, Pierluigi Nuzzo, Shahin Nazarian, Massoud Pedram. 638-641 [doi]
• Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level SynthesisZi Wang, Benjamin Carrión Schäfer. 642-645 [doi]
• Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoTHela Belhadj Amor, Carolynn Bernier. 646-649 [doi]
• Taming Data Caches for Predictable Execution on GPU-based SoCsBjörn Forsberg, Luca Benini, Andrea Marongiu. 650-653 [doi]
• Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISAGiuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini. 654-657 [doi]
• vDARM: Dynamic Adaptive Resource Management for Virtualized Multiprocessor SystemsJianmin Qian, Jian Li, Ruhui Ma, Haibing Guan. 658-661 [doi]
• NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22 nm FD-SOIFabian Schuiki, Michael Schaffner, Luca Benini. 662-667 [doi]
• Coherently Attached Programmable Near-Memory Acceleration Platform and its application to Stencil ProcessingJan van Lunteren, Ronald Luijten, Dionysios Diamantopoulos, Florian Auernhammer, Christoph Hagleitner, Lorenzo Chelini, Stefano Corda, Gagandeep Singh. 668-673 [doi]
• Advanced 3D Technologies and Architectures for 3D Smart Image SensorsPascal Vivet, Gilles Sicard, Laurent Millet, Stéphane Chevobbe, Karim Ben Chehida, Luis Angel Cubero, Monte Alegre, Maxence Bouvier, Alexandre Valentian, Maria Lepecq, Thomas Dombek, Olivier Bichler, Sebastien Thuries, Didier Lattard, Cheramy Severine, Perrine Batude, Fabien Clermidy. 674-679 [doi]
• A Camera with Brain - Embedding Machine Learning in 3D SensorsBurhan Ahmad Mudassar, Priyabrata Saha, Yun Long, Mohammad Faisal Amir, Evan Gebhardt, Taesik Na, Jong Hwan Ko, Marilyn Wolf, Saibal Mukhopadhyay. 680-685 [doi]
• 2 - the Internet of Tiny Things: Realizing mm-Scale Sensors through 3D Die StackingSechang Oh, Minchang Cho, Xiao Wu 0002, Yejoong Kim, Li-Xuan Chuo, Wootaek Lim, Pat Pannuto, Suyoung Bang, Kaiyuan Yang, Hun-Seok Kim, Dennis Sylvester, David T. Blaauw. 686-691 [doi]
• Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning ApplicationsNing-Chi Huang, Szu-Ying Chen, Kai-Chiang Wu. 692-697 [doi]
• Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth TruncationIoannis Tsiokanos, Lev Mukhanov, Georgios Karakonstantis. 698-703 [doi]
• A Smart Fault Detection Scheme for Reliable Image Processing ApplicationsMatteo Biasielli, Cristiana Bolchini, Luca Cassano, Antonio Miele. 704-709 [doi]
• Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time EnforcementJordi Cardona, Carles Hernández, Jaume Abella, Francisco J. Cazorla. 710-715 [doi]
• FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO ProcessorsMehdi Alipour, Rakesh Kumar 0003, Stefanos Kaxiras, David Black-Schaffer. 716-721 [doi]
• Boosting SIMD Benefits through a Run-time and Energy Efficient DLP DetectionMichael Guilherme Jordan, Tiago Knorst, Julio Vicenzi, Mateus Beck Rutzig. 722-727 [doi]
• 2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware DetectionHossein Sayadi, Hosein Mohammadi Makrani, Sai Manoj Pudukotai Dinakarrao, Tinoosh Mohsenin, Avesta Sasan, Setareh Rafatirad, Houman Homayoun. 728-733 [doi]
• Secure Intermittent Computing Protocol: Protecting State Across Power LossArchanaa S. Krishnan, Charles Suslowicz, Daniel Dinu, Patrick Schaumont. 734-739 [doi]
• RiskiM: Toward Complete Kernel Protection with Hardware SupportDongil Hwang, Myonghoon Yang, Seongil Jeon, YoungHan Lee, Donghyun Kwon, Yunheung Paek. 740-745 [doi]
• SACHa: Self-Attestation of Configurable HardwareJo Vliegen, Md Masoom Rabbani, Mauro Conti, Nele Mentens. 746-751 [doi]
• Laelaps: An Energy-Efficient Seizure Detection Algorithm from Long-term Human iEEG Recordings without False AlarmsAlessio Burrello, Lukas Cavigelli, Kaspar Schindler, Luca Benini, Abbas Rahimi. 752-757 [doi]
• Automatic Time-Frequency Analysis of MRPs for Mind-controlled Mechatronic DevicesDaniela De Venuto, Giovanni Mezzina. 758-763 [doi]
• A Self-Learning Methodology for Epileptic Seizure Detection with Minimally-Supervised Edge LabelingDamian Pascual, Amir Aminifar, David Atienza. 764-769 [doi]
• GAN-Sec: Generative Adversarial Network Modeling for the Security Analysis of Cyber-Physical Production SystemsSujit Rokka Chhetri, Anthony Bahadir Lopez, Jiang Wan, Mohammad Abdullah Al Faruque. 770-775 [doi]
• Lightweight Node-level Malware Detection and Network-level Malware Confinement in IoT NetworksSai Manoj Pudukotai Dinakarrao, Hossein Sayadi, Hosein Mohammadi Makrani, Cameron Nowzari, Setareh Rafatirad, Houman Homayoun. 776-781 [doi]
• Incremental Online Verification of Dynamic Cyber-Physical SystemsLei Bu, Shaopeng Xing, Xinyue Ren, Yang Yang, Qixin Wang, Xuandong Li. 782-787 [doi]
• Self-Secured Control with Anomaly Detection and Recovery in Automotive Cyber-Physical SystemsKorosh Vatanparvar, Mohammad Abdullah Al Faruque. 788-793 [doi]
• Time-division Multiplexing Automata ProcessorJintao Yu, Hoang Anh Du Nguyen, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui. 794-799 [doi]
• Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked MemoryAlvin Oliver Glova, Itir Akgun, Shuangchen Li, Xing Hu, Yuan Xie. 800-805 [doi]
• Towards Cross-Platform Inference on Edge Devices with Emerging Neuromorphic ArchitectureShangyu Wu, Yi Wang, Amelie Chi Zhou, Rui Mao, Zili Shao, Tao Li. 806-811 [doi]
• Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order CoreRon Gabor, Yiannakis Sazeides, Arkady Bramnik, Alexandros Andreou, Chrysostomos Nicopoulos, Karyofyllis Patsidis, Dimitris Konstantinou, Giorgos Dimitrakopoulos. 812-817 [doi]
• LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data CachePedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla. 818-823 [doi]
• High-Integrity GPU Designs for Critical Real-Time Automotive SystemsSergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella. 824-829 [doi]
• Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSISun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang, Chutong Yang. 830-835 [doi]
• Optimizing the Energy Efficiency of Power Supply in Heterogeneous Multicore Chips with Integrated Switched-Capacitor ConvertersLu Wang, LeiLei Wang, Dejia Shang, Cheng Zhuo, Pingqiang Zhou. 836-841 [doi]
• Power Delivery Pathfinding for Emerging Die-to-Wafer Integration TechnologyAndrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Kambiz Samadi, Bangqi Xu. 842-847 [doi]
• Energy-Efficient Convolutional Neural Networks via Recurrent Data ReuseLuca Mocerino, Valerio Tenace, Andrea Calimera. 848-853 [doi]
• Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance AccumulationElham Cheshmikhani, Hamed Farbeh, Hossein Asadi. 854-859 [doi]
• UIMigrate: Adaptive Data Migration for Hybrid Non-Volatile Memory SystemsYujuan Tan, Baiping Wang, Zhichao Yan, Qiuwei Deng, Xianzhang Chen, Duo Liu. 860-865 [doi]
• Reducing Write Amplification for Inodes of Journaling File System using Persistent MemoryChaoshu Yang, Duo Liu, Xianzhang Chen, Runyu Zhang, Wenbin Wang, Moming Duan, Yujuan Tan. 866-871 [doi]
• Cost/Privacy Co-optimization in Smart Energy GridsAlma Pröbstl, Sangyoung Park, Sebastian Steinhorst, Samarjit Chakraborty. 872-877 [doi]
• A Low-Complexity Framework for Distributed Energy Market Targeting Smart-GridKostas Siozios, Stylianos Siskos. 878-883 [doi]
• Irradiance-Driven Partial Reconfiguration of PV PanelsDaniele Jahier Pagliari, Sara Vinco, Enrico Macii, Massimo Poncino. 884-889 [doi]
• Better Late Than Never : Verification of Embedded Systems After DeploymentMartin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler. 890-895 [doi]
• Efficient Computation of Deadline-Miss Probability and Potential PitfallsKuan-Hsun Chen, Niklas Ueter, Georg von der Bruggen, Jian-Jia Chen. 896-901 [doi]
• FAdeML: Understanding the Impact of Pre-Processing Noise Filtering on Adversarial Machine LearningFaiq Khalid, Muhammad Abdullah Hanif, Semeen Rehman, Junaid Qadir, Muhammad Shafique 0001. 902-907 [doi]
• Real-Time Anomalous Branch Behavior Inference with a GPU-inspired Engine for Machine Learning ModelsHyunyoung Oh, Hayoon Yi, Hyeokjun Choe, Yeongpil Cho, Sungroh Yoon, Yunheung Paek. 908-913 [doi]
• TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area FootprintImran Hafeez Abbassi, Faiq Khalid, Semeen Rehman, Awais Mehmood Kamboh, Axel Jantsch, Siddharth Garg, Muhammad Shafique 0001. 914-919 [doi]
• Non-Intrusive Self-Test Library for Automotive Critical Applications: Constraints and SolutionsPaolo Bernardi, Riccardo Cantoro, Andrea Floridia, Davide Piumatti, C. Pogonea, Annachiara Ruospo, E. Sanchez, S. De Luca, Alessandro Sansonetti. 920-923 [doi]
• Dependency-Resolving Intra-Unit Pipeline Architecture for High-Throughput MultipliersJihee Seo, Dae-Hyun Kim. 924-927 [doi]
• A Hardware-Efficient Logarithmic Multiplier with Improved AccuracyMohammad Saeed Ansari, Bruce F. Cockburn, Jie Han 0001. 928-931 [doi]
• Lightweight hardware support for selective coherence in heterogeneous manycore acceleratorsAlessandro Cilardo, Mirko Gagliardi, Vincenzo Scotti. 932-935 [doi]
• Functional Analysis Attacks on Logic LockingDeepak Sirone, Pramod Subramanyan. 936-939 [doi]
• SigAttack: New High-level SAT-based Attack on Logic EncryptionsYuanqi Shen, You Li, Shuyu Kong, Amin Rezaei, Hai Zhou. 940-943 [doi]
• ZeroPowerTouch: Zero-Power Smart Receiver for Touch Communication and Sensing in Wearable ApplicationsPhilipp Mayer, Raphael Strebel, Michele Magno. 944-947 [doi]
• Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy MonitorsLorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi, Amir Aminifar, David Atienza, Leila Cammoun, Philippe Ryvlin. 948-951 [doi]
• An indoor localization system to detect areas causing the freezing of gait in ParkinsoniansFlorenc Demrozi, Vladislav Bragoi, Federico Tramarin, Graziano Pravadelli. 952-955 [doi]
• Assembly-Related Chip/Package Co-Design of Heterogeneous Systems Manufactured by Micro-Transfer PrintingRobert Fischbach, Tilman Horst, Jens Lienig. 956-959 [doi]
• Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and PowerDipan Kumar Mandal, Srivatsava Jandhyala, Om J. Omer, Gurpreet S. Kalsi, Biji George, Gopi Neela, Santhosh Kumar Rethinagiri, Sreenivas Subramoney, Lance Hacking, Jim Radford, Eagle Jones, Belliappa Kuttanna, Hong Wang. 960-963 [doi]
• CapsAcc: An Efficient Hardware Accelerator for CapsuleNets with Data ReuseAlberto Marchisio, Muhammad Abdullah Hanif, Muhammad Shafique 0001. 964-967 [doi]
• SDCNN: An Efficient Sparse Deconvolutional Neural Network Accelerator on FPGAJung-Woo Chang, Keon-Woo Kang, Suk-Ju Kang. 968-971 [doi]
• A Fine-Grained Soft Error Resilient Architecture under Power ConsiderationsSajjad Hussain, Muhammad Shafique, Jörg Henkel. 972-975 [doi]
• Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function UnitsRafail Psiakis, Angeliki Kritikakou, Olivier Sentieys. 976-979 [doi]
• Adaptive Word Reordering for Low-Power Inter-Chip CommunicationEleni Maragkoudaki, Przemyslaw Mroszczyk, Vasilis F. Pavlidis. 980-983 [doi]
• Machine-Learning-Driven Matrix Ordering for Power Grid AnalysisGanqu Cui, Wenjian Yu, Xin Li, Zhiyu Zeng, Ben Gu. 984-987 [doi]
• Assertion-Based Verification through Binary InstrumentationEnzo Brignon, Laurence Pierre. 988-991 [doi]
• Hardware and firmware verification and validation: an algorithm-to-firmware development methodologyHenry Cox, Harry H. Chen. 992-993 [doi]
• Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution CheckingMohammad Rahmani Fadiheh, Dominik Stoffel, Clark Barrett, Subhasish Mitra, Wolfgang Kunz. 994-999 [doi]
• Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case StudyEshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad R. Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark Barrett, Wolfgang Ecker, Subhasish Mitra. 1000-1005 [doi]
• Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCsGeorges G. E. Gielen, Nektar Xama, Karthik Ganesan, Subhasish Mitra. 1006-1009 [doi]
• On Functional Test Generation for Deep Neural Network IPsBo Luo, Yu Li, Lingxiao Wei, Qiang Xu 0001. 1010-1015 [doi]
• On Secure Data Flow in Reconfigurable Scan NetworksPascal Raiola, Benjamin Thiemann, Jan Burchard, Ahmed Atteya, Natalia Lylina, Hans-Joachim Wunderlich, Bernd Becker 0001, Matthias Sauer 0002. 1016-1021 [doi]
• Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability GuidelinesNaixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman. 1022-1027 [doi]
• Test Pattern Generation for Approximate Circuits Based on Boolean SatisfiabilityAnteneh Gebregiorgis, Mehdi Baradaran Tahoori. 1028-1033 [doi]
• Adaptive Vehicle Detection for Real-time Autonomous Driving SystemMaryam Hemmati, Morteza Biglari-Abhari, Smaïl Niar. 1034-1039 [doi]
• An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccelXin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng 0001. 1040-1045 [doi]
• Accelerating Itemset Sampling using Satisfiability Constraints on FPGAMael Gueguen, Olivier Sentieys, Alexandre Termier. 1046-1051 [doi]
• DS-Cache: A Refined Directory Entry Lookup Cache with Prefix-Awareness for Mobile DevicesLei Han, Bin Xiao, Xuwei Dong, Zhaoyan Shen, Zili Shao. 1052-1057 [doi]
• Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore AcceleratorsSheng Ma, Yang Guo, Shenggang Chen, Libo Huang, Zhiying Wang. 1058-1063 [doi]
• QBLK: Towards Fully Exploiting the Parallelism of Open-Channel SSDsHongwei Qin, Dan Feng 0001, Wei Tong, Jingning Liu, Yutong Zhao. 1064-1069 [doi]
• A Methodology for Comparative Analysis of Collaborative Robots for Industry 4.0Federica Ferraguti, Andrea Pertosa, Cristian Secchi, Cesare Fantuzzi, Marcello Bonfé. 1070-1075 [doi]
• Hybrid Sensing Approach For Coded Modulation Time-of-Flight CamerasArmin Schoenlieb, Hannes Plank, Christian Steger, Gerald Holweg, Norbert Druml. 1076-1081 [doi]
• Communication-Computation co-Design of Decentralized Task Chain in CPS ApplicationsSeyyed Ahmad Razavi, Eli Bozorgzadeh, Solmaz S. Kia. 1082-1087 [doi]
• Resource Manager for Scalable Performance in ROS Distributed EnvironmentsDaisuke Fukutomi, Takuya Azumi, Shinpei Kato, Nobuhiko Nishio. 1088-1093 [doi]
• Self-Supervised Quantization of Pre-Trained Neural Networks for Multiplierless AccelerationSebastian Vogel, Jannik Springer, Andre Guntoro, Gerd Ascheid. 1094-1099 [doi]
• Multi-objective Precision Optimization of Deep Neural Networks for Edge DevicesNhut-Minh Ho, Ramesh Vaddi, Weng-Fai Wong. 1100-1105 [doi]
• Towards Design Space Exploration and Optimization of Fast Algorithms for Convolutional Neural Networks (CNNs) on FPGAsAfzal Ahmad, Muhammad Adeel Pasha. 1106-1111 [doi]
• Accelerating Local Binary Pattern Networks with Software-Programmable FPGAsJeng-Hau Lin, Atieh Lotfi, Vahideh Akhlaghi, Zhuowen Tu, Rajesh K. Gupta 0001. 1112-1117 [doi]
• Transient Key-based Obfuscation for HLS in an Untrusted Cloud EnvironmentHannah Badier, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat. 1118-1123 [doi]
• High-Level Synthesis of Benevolent TrojansChristian Pilato, Kanad Basu, Mohammed Shayan, Francesco Regazzoni, Ramesh Karri. 1124-1129 [doi]
• Machine Learning Based Routing Congestion Prediction in FPGA High-Level SynthesisJieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang. 1130-1135 [doi]
• Protecting RISC-V Processors against Physical AttacksMario Werner, Robert Schilling, Thomas Unterluggauer, Stefan Mangard. 1136-1141 [doi]
• Sanctorum: A lightweight security monitor for secure enclavesIlia A. Lebedev, Kyle Hogan, Jules Drean, David Kohlbrenner, Dayeol Lee, Krste Asanovic, Dawn Song, Srinivas Devadas. 1142-1147 [doi]
• Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-VTim Fritzmann, Uzair Sharif, Daniel Müller-Gritschneder, Cezar Reinbrecht, Ulf Schlichtmann, Johanna Sepúlveda. 1148-1153 [doi]
• A Security Architecture for RISC-V based IoT DevicesLukas Auer, Christian Skubich, Matthias Hiller. 1154-1159 [doi]
• Real-time Detection and Localization of DoS Attacks in NoC based SoCsSubodha Charles, Yangdi Lyu, Prabhat Mishra. 1160-1165 [doi]
• High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement LearninKe Wang, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu. 1166-1171 [doi]
• Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor ArchitectureKaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li. 1172-1177 [doi]
• Advance Virtual Channel ReservationBoqian Wang, Zhonghai Lu. 1178-1183 [doi]
• SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUsSohan Lal, Jan Lucas, Ben H. H. Juurlink. 1184-1189 [doi]
• LoSCache: Leveraging Locality Similarity to Build Energy-Efficient GPU L2 CacheJingweijia Tan, Kaige Yan, Shuaiwen Leon Song, Xin Fu. 1190-1195 [doi]
• LBICA: A Load Balancer for I/O Cache ArchitecturesSaba Ahmadian, Reza Salkhordeh, Hossein Asadi. 1196-1201 [doi]
• AURIX TC277 Multicore Contention Model Integration for Automotive ApplicationsEnrico Mezzetti, Luca Barbina, Jaume Abella, Stefania Botta, Francisco J. Cazorla. 1202-1203 [doi]
• Seamless SoC Verification Using Virtual Platforms: An Industrial Case StudyKyungsu Kang, Sangho Park, Byeongwook Bae, Jungyun Choi, SungGil Lee, Byunghoon Lee, Jong-Bae Lee. 1204-1205 [doi]
• Multicore Early Design Stage Guaranteed Performance Estimates for the Space DomainMikel Fernández, Gabriel Fernandez, Jaume Abella, Francisco J. Cazorla. 1206-1207 [doi]
• Polar Code Decoder FrameworkTimo Lehnigk-Emden, Matthias Alles, Claus Kestel, Norbert Wehn. 1208-1209 [doi]
• Increasing Accuracy of Timing Models: From CPA to CPA+Leonie Köhler, Borislav Nikolic, Rolf Ernst, Marc Boyer. 1210-1215 [doi]
• Scratchpad Memories with OwnershipMartin Schoeberl, Tórur Biskopsto Strøm, Oktay Baris, Jens Sparsø. 1216-1221 [doi]
• A Container-based DoS Attack-Resilient Control Framework for Real-Time UAV SystemsJiyang Chen, Zhiwei Feng, Jen-Yang Wen, Bo Liu, Lui Sha. 1222-1227 [doi]
• An Exact Schedulability Test for Non-Preemptive Self-Suspending Real-Time TasksBeyazit Yalcinkaya, Mitra Nasri, Björn B. Brandenburg. 1228-1233 [doi]
• IBM's Qiskit Tool Chain: Working with and Developing for Real Quantum ComputersRobert Wille, Rod Van Meter, Yehuda Naveh. 1234-1240 [doi]
• An Efficient Mapping Approach to Large-Scale DNNs on Multi-FPGA ArchitecturesWentai Zhang, Jiaxi Zhang, Minghua Shen, Guojie Luo, Nong Xiao. 1241-1244 [doi]
• A Write-Efficient Cache Algorithm based on Macroscopic Trend for NVM-based Read CacheNing Bao, Yunpeng Chai, Xiao Qin 0001. 1245-1248 [doi]
• SRAM Design Exploration with Integrated Application-Aware Aging AnalysisAlexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Sani R. Nassif. 1249-1252 [doi]
• From Multi-Level to Abstract-Based Simulation of a Production LineStefano Centomo, Enrico Fraccaroli, Marco Panato. 1253-1256 [doi]
• Accurate Dynamic Modelling of Hydraulic ServomechanismsManuel Pencelli, Renzo Villa, Alfredo Argiolas, Gianni Ferretti, Marta Niccolini, Matteo Ragaglia, Paolo Rocco, Andrea Maria Zanchettin. 1257-1260 [doi]
• Planning with Real-Time Collision Avoidance for Cooperating Agents under Rigid Body ConstraintsNicola Piccinelli, Federico Vesentini, Riccardo Muradore. 1261-1264 [doi]
• The Case for Exploiting Underutilized Resources in Heterogeneous Mobile ArchitecturesChen-Ying Hsieh, Ardalan Amiri Sani, Nikil D. Dutt. 1265-1268 [doi]
• Online Rare Category Detection for Edge ComputingYufei Cui, Qiao Li, Sarana Nutanong, Chun Jason Xue. 1269-1272 [doi]
• RAGra: Leveraging Monolithic 3D ReRAM for Massively-Parallel Graph ProcessingYu Huang, Long Zheng 0003, Xiaofei Liao, Hai Jin 0001, Pengcheng Yao, Chuangyi Gui. 1273-1276 [doi]
• Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer VisionLorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Martin Manzinger, Wolfgang Ecker, Robert Wille. 1277-1280 [doi]
• Practical Causality Handling for Synchronous LanguagesSteven Smyth, Alexander Schulz-Rosengarten, Reinhard von Hanxleden. 1281-1284 [doi]
• Application Performance Prediction and Optimization Under Cache Allocation TechnologyYeseong Kim, Ankit More, Emily Shriver, Tajana Rosing. 1285-1288 [doi]
• Generalized Matrix Factorization Techniques for Approximate Logic SynthesisSoheil Hashemi, Sherief Reda. 1289-1292 [doi]
• CARS: A Multi-layer Conflict-Aware Request Scheduler for NVMe SSDsTianming Yang, Ping Huang, Weiying Zhang, Haitao Wu, Longxin Lin. 1293-1296 [doi]
• Queue Based Memory Management Unit for Heterogeneous MPSoCsRobert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis. 1297-1300 [doi]
• Embedded Systems' Automation following OMG's Model Driven Architecture VisionWolfgang Ecker, Keerthikumara Devarajegowda, Michael Werner, Zhao Han, Lorenzo Servadei. 1301-1306 [doi]
• A Brief Survey of Algorithms, Architectures, and Challenges toward Extreme-scale Graph AnalyticsAnanth Kalyanaraman, Partha Pratim Pande. 1307-1312 [doi]
• A Parallel Graph Environment for Real-World Data Analytics WorkflowsVito Giovanni Castellana, Maurizio Drocco, John Feo, Jesun Sahariar Firoz, Thejaka Amila Kanewala, Andrew Lumsdaine, Joseph B. Manzano, Andres Marquez, Marco Minutoli, Joshua Suetterlein, Antonino Tumeo, Marcin Zalewski. 1313-1318 [doi]
• *Alexander van der Grinten, Henning Meyerhenke. 1319-1324 [doi]
• Identifying the Most Reliable Collaborative Workload Distribution in Heterogeneous DevicesGabriel Piscoya Davila, Daniel Oliveira, Philippe O. A. Navaux, Paolo Rech. 1325-1330 [doi]
• CE-Based Optimization for Real-time System Availability under Learned Soft Error RateLiying Li, Tongquan Wei, Junlong Zhou, Mingsong Chen, Xiaobo Sharon Hu. 1331-1336 [doi]
• A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Wafer-Level NoCZhongsheng Chen, Ying Zhang, Zebo Peng, Jianhui Jiang. 1337-1342 [doi]
• CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICsBenjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak. 1343-1348 [doi]
• Compiling Permutations for Superconducting QPUsMathias Soeken, Fereshte Mozafari, Bruno Schmitt, Giovanni De Micheli. 1349-1354 [doi]
• Stochastic Computing with Integrated OpticsHassnaa El-Derhalli, Sébastien Le Beux, Sofiene Tahar. 1355-1360 [doi]
• Inkjet-Printed True Random Number Generator based on Additive Resistor TuningAhmet Turan Erozan, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori. 1361-1366 [doi]
• HotR: Alleviating Read/Write Interference with Hot Read Data Replication for Flash StorageSuzhen Wu, Weiwei Zhang, Bo Mao, Hong Jiang. 1367-1372 [doi]
• RAFS: A RAID-Aware File System to Reduce the Parity Update Overhead for SSD RAIDChenlei Tang, Jiguang Wan, Yifeng Zhu, Zhiyuan Liu, Peng Xu, Fei Wu, Changsheng Xie. 1373-1378 [doi]
• Automatic data placement for CPU-FPGA heterogeneous multiprocessor System-on-ChipsShiqing Li, Yixun Wei, Lei Ju. 1379-1384 [doi]
• A Runtime Resource Management Policy for OpenCL Workloads on Heterogeneous MulticoresDaniele Angioletti, Francesco Bertani, Cristiana Bolchini, Francesco Cerizzi, Antonio Miele. 1385-1390 [doi]
• DMRM: Distributed Market-Based Resource Management of Edge Computing SystemsManolis Katsaragakis, Dimosthenis Masouros, Vasileios Tsoutsouras, Farzad Samie, Lars Bauer, Jörg Henkel, Dimitrios Soudris. 1391-1396 [doi]
• Goal-Driven Autonomy for Efficient On-chip Resource Management: Transforming Objectives to GoalsElham Shamsa, Anil Kanduri, Amir M. Rahmani, Pasi Liljeberg, Axel Jantsch, Nikil D. Dutt. 1397-1402 [doi]
• Scrub Unleveling: Achieving High Data Reliability at Low Scrubbing CostTianming Jiang, Ping Huang, Ke Zhou 0001. 1403-1408 [doi]
• Learning to infer: RL-based search for DNN primitive selection on Heterogeneous Embedded SystemsMiguel de Prado, Nuria Pazos, Luca Benini. 1409-1414 [doi]
• Memory Trojan Attack on Neural Network AcceleratorsYang Zhao, Xing Hu, Shuangchen Li, Jing Ye, Lei Deng, Yu Ji, Jianyu Xu, Dong Wu, Yuan Xie. 1415-1420 [doi]
• Deep Positron: A Deep Neural Network Using the Posit Number SystemZachariah Carmichael, Hamed Fatemi Langroudi, Char Khazanov, Jeffrey Lillie, John L. Gustafson, Dhireesha Kudithipudi. 1421-1426 [doi]
• Learning to Skip Ineffectual Recurrent Computations in LSTMsArash Ardakani, Zhengyun Ji, Warren J. Gross. 1427-1432 [doi]
• Specifying and Evaluating Quality Metrics for Vision-based Perception SystemsAnand Balakrishnan 0001, Aniruddh G. Puranic, Xin Qin, Adel Dokhanchi, Jyotirmoy V. Deshmukh, Heni Ben Amor, Georgios Fainekos. 1433-1438 [doi]
• Cross-Layer Interactions in CPS for Performance and CertificationSamarjit Chakraborty, James H. Anderson, Martin Becker 0001, Helmut Graeb, Samiran Halder, Ravindra Metta, Lothar Thiele, Stavros Tripakis, Anand Yeolekar. 1439-1444 [doi]
• Towards verified programming of embedded devicesJean-Pierre Talpin, Jean-Joseph Marty, Shravan Narayan, Deian Stefan, Rajesh Gupta. 1445-1450 [doi]
• Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid AutomataAhmad Tarraf, Lars Hedrich. 1451-1456 [doi]
• Nubolic Simulation of AMS Systems with Data Flow and Discrete Event ModelsCarna Zivkovic, Christoph Grimm 0001. 1457-1462 [doi]
• Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural NetworkShuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng 0001. 1463-1468 [doi]
• Rebooting Our Computing ModelsPatsy Cadareanu, N. Reddy C, Carmen G. Almudever, A. Khanna, A. Raychowdhury, S. Datta, Koen Bertels, V. Narayanan, M. Di Ventra, Pierre-Emmanuel Gaillardon. 1469-1476 [doi]
• NeuADC: Neural Network-Inspired RRAM-Based Synthesizable Analog-to-Digital Conversion with Reconfigurable Quantization SupportWeidong Cao, Xin He, Ayan Chakrabarti, Xuan Zhang. 1477-1482 [doi]
• HolyLight: A Nanophotonic Accelerator for Deep Learning in Data CentersWeichen Liu, Wenyang Liu, Yichen Ye, Qian Lou, Yiyuan Xie, Lei Jiang. 1483-1488 [doi]
• Transfer and Online Reinforcement Learning in STT-MRAM Based Embedded Systems for Autonomous DronesInsik Yoon, Malik Aqeel Anwar, Titash Rakshit, Arijit Raychowdhury. 1489-1494 [doi]
• AIX: A high performance and energy efficient inference accelerator on FPGA for a DNN-based commercial speech recognitionMinwook Ahn, Seok Joong Hwang, Wonsub Kim, Seungrok Jung, Yeonbok Lee, Mookyoung Chung, Woohyung Lim, Young-Joon Kim. 1495-1500 [doi]
• VM-aware Flush Mechanism for Mitigating Inter-VM I/O InterferenceTae Hyung Lee, Minho Lee, Young Ik Eom. 1501-1506 [doi]
• An Efficient Bit-Flip Resilience Optimization Method for Deep Neural NetworksChristoph Schorn, Andre Guntoro, Gerd Ascheid. 1507-1512 [doi]
• Approximation-aware Task Deployment on Asymmetric Multicore ProcessorsLei Mo, Angeliki Kritikakou, Olivier Sentieys. 1513-1518 [doi]
• ∗Mohamed Ibrahim, Bhargab B. Bhattacharya, Krishnendu Chakrabarty. 1519-1524 [doi]
• Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel StorageZhisheng Chen, Xing Huang, Wenzhong Guo, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann. 1525-1530 [doi]
• Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic DevicesYu-Huei Lin, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann. 1531-1536 [doi]
• Analyzing GEDF Scheduling for Parallel Real-Time Tasks with Arbitrary DeadlinesXu Jiang, Nan Guan, Di Liu, Weichen Liu. 1537-1542 [doi]
• Simple and General Methods for Fixed-Priority Schedulability in Optimization ProblemsPaolo Pazzaglia, Alessandro Biondi, Marco Di Natale. 1543-1548 [doi]
• Hard Real-Time Scheduling of Streaming Applications Modeled as Cyclic CSDF GraphsSobhan Niknam, Peng Wang, Todor P. Stefanov. 1549-1554 [doi]
• Thermal-Awareness in a Soft Error Tolerant ArchitectureSajjad Hussain, Muhammad Shafique, Jörg Henkel. 1555-1558 [doi]
• A software-level Redundant MultiThreading for Soft/Hard Error Detection and RecoveryHwisoo So, Moslem Didehban, Aviral Shrivastava, Kyoungwoo Lee. 1559-1562 [doi]
• Common-Mode Failure Mitigation: Increasing Diversity through High-Level SynthesisFarah Naz Taher, Matthew Joslin, Anjana Balachandran, Zhiqi Zhu, Benjamin Carrión Schäfer. 1563-1566 [doi]
• Exploiting Wavelength Division Multiplexing for Optical Logic SynthesisZheng Zhao, Derong Liu 0002, Zhoufeng Ying, Biying Xu, Chenghao Feng, Ray T. Chen, David Z. Pan. 1567-1570 [doi]
• IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTMDimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar. 1571-1574 [doi]
• Using Machine Learning for Quality Configurable Approximate ComputingMahmoud Masadeh, Osman Hasan, Sofiène Tahar. 1575-1578 [doi]
• Prediction-Based Task Migration on S-NUCA Many-CoresMartin Rapp, Anuj Pathania, Tulika Mitra, Jörg Henkel. 1579-1582 [doi]
• Design of Hardware-Friendly Memory Enhanced Neural NetworksAnn Franchesca Laguna, Michael Niemier, Xiaobo Sharon Hu. 1583-1586 [doi]
• Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGASeongsik Park, Jaehee Jang, Sei Joon Kim, Sungroh Yoon. 1587-1590 [doi]
• HDCluster: An Accurate Clustering Using Brain-Inspired High-Dimensional ComputingMohsen Imani, Yeseong Kim, Thomas Worley, Saransh Gupta, Tajana Rosing. 1591-1594 [doi]
• Finding All DC Operating Points Using Interval Arithmetic Based Verification AlgorithmsItrat A. Akhter, Justin Reiher, Mark R. Greenstreet. 1595-1598 [doi]
• GENIE: QoS-guided Dynamic Scheduling for CNN-based Tasks on SME ClustersZhaoyun Chen, Lei Luo, Haoduo Yang, Jie Yu, Mei Wen, Chunyuan Zhang. 1599-1602 [doi]
• A Pulse Width Modulation based Power-elastic and Robust Mixed-signal Perceptron DesignSergey Mileiko, Rishad A. Shafik, Alex Yakovlev, Jonathan Edwards. 1603-1606 [doi]
• Fault Localization in Programmable Microfluidic DevicesAlessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann. 1607-1610 [doi]
• Thermal Sensing Using Micro-ring Resonators in Optical Network-on-ChipWeichen Liu, Mengquan Li, Wanli Chang, Chunhua Xiao, Yiyuan Xie, Nan Guan, Lei Jiang. 1611-1614 [doi]
• Adiabatic Implementation of Manchester Encoding for Passive NFC SystemSachin Maheshwari, Izzet Kale. 1615-1618 [doi]
• Semantic Integration Platform for Cyber-Physical System DesignQishen Zhang, Tamás Kecskés, Ted Bapty, Janos Sztipanovits. 1619-1624 [doi]
• Worst-Case Cause-Effect Reaction Latency in Systems with Non-Blocking CommunicationJakaria Abdullah, Gaoyang Dai, Wang Yi 0001. 1625-1630 [doi]
• Harmonizing Safety, Security and Performance Requirements in Embedded SystemsLudovic Apvrille, Letitia W. Li. 1631-1636 [doi]
• A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching LatticesLevent Aksoy, Mustafa Altun. 1637-1642 [doi]
• Scalable Boolean Methods in a Modern Synthesis FlowEleonora Testa, Luca Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 1643-1648 [doi]
• On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact SynthesisHeinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken. 1649-1654 [doi]
• Approximate Logic Synthesis by SymmetrizationAnna Bernasconi 0001, Valentina Ciriani, Tiziano Villa. 1655-1660 [doi]
• Package and Chip Accelerated Aging Methods for Power MOSFET Reliability EvaluationTing-You Lin, Chauchin Su, Chung-Chih Hung, Karuna Nidhi, Chily Tu, Shao-Chang Huang. 1661-1666 [doi]
• Bayesian Optimized Importance Sampling for High Sigma Failure Rate EstimationDennis D. Weller, Michael Hefenbrock, Mohammad Saber Golanbari, Michael Beigl, Mehdi Baradaran Tahoori. 1667-1672 [doi]
• Wafer-Level Adaptive Vmin Calibration Seed ForecastingConstantinos Xanthopoulos, Deepika Neethirajan, Sirish Boddikurapati, Amit Nahar, Yiorgos Makris. 1673-1678 [doi]
• Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power ApplicationsAibin Yan, Yuanjie Hu, Jie Song, Xiaoqing Wen. 1679-1684 [doi]
• Dynamic Scheduling on Heterogeneous MulticoresAyobami Edun, Ruben Vazquez, Ann Gordon-Ross, Greg Stitt. 1685-1690 [doi]
• Selecting the Optimal Energy Point in Near-Threshold ComputingSami Salamin, Hussam Amrouch, Jörg Henkel. 1691-1696 [doi]
• Exploration and Design of Low-Energy Logic Cells for 1 kHz Always-on SystemsMaxime Feyerick, Jaro De Roose, Marian Verhelst. 1697-1702 [doi]
• Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based PlatformsValentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Stefano Mattoccia. 1703-1708 [doi]
• RDF: Reconfigurable DataflowPascal Fradet, Alain Girault, Ruby Krishnaswamy, Xavier Nicollin, Arash Shafiei 0001. 1709-1714 [doi]
• Probabilistic State-Based RT-Analysis of SDFGs on MPSoCs with Shared Memory CommunicationRalf Stemmer, Henning Schlender, Maher Fakih, Kim Grüttner, Wolfgang Nebel. 1715-1720 [doi]
• Speculative Temporal Decoupling Using fork()Matthias Jung 0001, Frank Schnicke, Markus Damm, Thomas Kuhn, Norbert Wehn. 1721-1726 [doi]
• When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain TrojansXiaolong Guo, Huifeng Zhu, Yier Jin, Xuan Zhang. 1727-1732 [doi]
• Fourℚ on ASIC: Breaking Speed Records for Elliptic Curve Scalar MultiplicationHiromitsu Awano, Makoto Ikeda. 1733-1738 [doi]
• DArL: Dynamic Parameter Adjustment for LWE-based Secure InferenceSong Bian, Masayuki Hiromoto, Takashi Sato. 1739-1744 [doi]
• Timing Violation Induced Faults in Multi-Tenant FPGAsDina Mahmoud, Mirjana Stojilovic. 1745-1750 [doi]
• Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic ComputingShuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann. 1751-1756 [doi]
• Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream ProcessingS. Rasoul Faraji, M. Hassan Najafi, Bingzhe Li, David J. Lilja, Kia Bazargan. 1757-1762 [doi]
• RED: A ReRAM-based Deconvolution AcceleratorZichen Fan, Ziru Li, Bing Li, Yiran Chen, Hai Helen Li. 1763-1768 [doi]
• Design of Reliable DNN Accelerator with Un-reliable ReRAMYun Long, Xueyuan She, Saibal Mukhopadhyay. 1769-1774 [doi]