The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor

Don Weiss, John J. Wuu, Victor Chin. The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor. J. Solid-State Circuits, 37(11):1523-1529, 2002. [doi]

Authors

Don Weiss

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John J. Wuu

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Victor Chin

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