Don Weiss, John J. Wuu, Victor Chin. The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor. J. Solid-State Circuits, 37(11):1523-1529, 2002. [doi]
@article{WeissWC02,
title = {The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor},
author = {Don Weiss and John J. Wuu and Victor Chin},
year = {2002},
doi = {10.1109/JSSC.2002.802354},
url = {https://doi.org/10.1109/JSSC.2002.802354},
researchr = {https://researchr.org/publication/WeissWC02},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {37},
number = {11},
pages = {1523-1529},
}