3-D memory organization and performance analysis for multi-processor network-on-chip architecture

Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerasekera, Hannu Tenhunen. 3-D memory organization and performance analysis for multi-processor network-on-chip architecture. In IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009. pages 1-7, IEEE, 2009. [doi]

@inproceedings{WeldezionLWT09,
  title = {3-D memory organization and performance analysis for multi-processor network-on-chip architecture},
  author = {Awet Yemane Weldezion and Zhonghai Lu and Roshan Weerasekera and Hannu Tenhunen},
  year = {2009},
  doi = {10.1109/3DIC.2009.5306593},
  url = {http://dx.doi.org/10.1109/3DIC.2009.5306593},
  tags = {architecture, analysis},
  researchr = {https://researchr.org/publication/WeldezionLWT09},
  cites = {0},
  citedby = {0},
  pages = {1-7},
  booktitle = {IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009},
  publisher = {IEEE},
}