A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders - researchr publication authors

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Michael Wieckowski, Martin Margala. A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders. In Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA. pages 251-254, IEEE, 2004. [doi]

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