Michael Wieckowski, Martin Margala. A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders. In Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA. pages 251-254, IEEE, 2004. [doi]
@inproceedings{WieckowskiM04,
title = {A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders},
author = {Michael Wieckowski and Martin Margala},
year = {2004},
doi = {10.1109/SOCC.2004.1362425},
url = {http://dx.doi.org/10.1109/SOCC.2004.1362425},
researchr = {https://researchr.org/publication/WieckowskiM04},
cites = {0},
citedby = {0},
pages = {251-254},
booktitle = {Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA},
publisher = {IEEE},
isbn = {0-7803-8445-8},
}