Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic - researchr publication

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Yuk Wong, Zhenjiang Dong, Wei Zhang. Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA, July 7-9, 2021. pages 218-223, IEEE, 2021. [doi]

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