Abstract is missing.
- A Fully Digital Foreground Calibration Technique of A Flash ADCShatadal Chatterjee, Maryaradhiya Daimari, Sounak Roy. 1-6 [doi]
- An Adaptive Lockstep Architecture for Mixed-Criticality SystemsFabian Kempf, Thomas Hartmann, Steffen Baehr, Jürgen Becker 0001. 7-12 [doi]
- Real-Time IC Aging Prediction via On-Chip SensorsKe Huang, Md Toufiq Hasan Anik, Xinqiao Zhang, Naghmeh Karimi. 13-18 [doi]
- A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video ApplicationsShiv Chandra Kumar, Siddharth R. K., Nithin Kumar Y. B., M. H. Vasantha. 19-24 [doi]
- ILP-Based Global Routing Optimization with Cell MovementsTiago Augusto Fontana, Erfan Aghaeekiasaraee, Renan Netto, Sheiny Fabre Almeida, Upma Gandh, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat, José Luís Güntzel. 25-30 [doi]
- A Comparative Study of Specification Mining Methods for SoC Communication TracesMd Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang. 31-36 [doi]
- Reverse Engineering Register to Variable Mapping in High-level SynthesisMohammed Abderehman, Rupak Gupta, Chandan Karfa. 37-42 [doi]
- Resource and Performance Estimation for CNN Models using Machine LearningMasoud Shahshahani, Dinesh Bhatia. 43-48 [doi]
- Stochastic Number Generators with Minimum Probability Conversion CircuitsChris Collinsworth, Sayed Ahmad Salehi. 49-54 [doi]
- Counter Random Gradient Descent Bit-Flipping Decoder for LDPC CodesKeyue Deng, Hangxuan Cui, Jun Lin, Zhongfeng Wang. 55-60 [doi]
- Depth Optimized Synthesis of Symmetric Boolean FunctionsMartha Schnieber, Saman Fröhlich, Rolf Drechsler. 61-66 [doi]
- A Multi-Context Neural Core Design for Reconfigurable Neuromorphic ArraysAdam Z. Foshie, Nishith N. Chakraborty, John J. Murray, Tanner J. Fowler, Mst Shamim Ara Shawkat, Garrett S. Rose. 67-72 [doi]
- A Terabit Hybrid FPGA-ASIC Platform for Switch VirtualizationMateus Saquetti, Raphael M. Brum, Bruno Zatt, Samuel Pagliarini, Weverton Cordeiro, José Rodrigo Azambuja. 73-78 [doi]
- Crosstalk Logic Circuits with Built-in MemoryNaveen Kumar Macha, Prerana Samant, Mostafizur Rahman. 79-83 [doi]
- SpamHD: Memory-Efficient Text Spam Detection using Brain-Inspired Hyperdimensional ComputingRahul Thapa, Bikal Lamichhane, Dongning Ma, Xun Jiao. 84-89 [doi]
- HDXplore: Automated Blackbox Testing of Brain-Inspired Hyperdimensional ComputingRahul Thapa, Dongning Ma, Xun Jiao. 90-95 [doi]
- BDD Variable Ordering for Minimizing Power Consumption of Optical Logic CircuitsRyosuke Matsuo, Shin-ichi Minato. 96-101 [doi]
- Scaling Constraints for Memristor-based Programmable Interconnect in Reconfigurable Computing ArraysJohn J. Murray, Adam Z. Foshie, Mst Shamim Ara Shawkat, Garrett S. Rose. 102-107 [doi]
- Tile Architecture and Hardware Implementation for Computation-in-MemoryMahdi Zahedi, Remon van Duijnen, Stephan Wong, Said Hamdioui. 108-113 [doi]
- On Preventing SAT Attack with Decoy Key-InputsQuang-Linh Nguyen, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre. 114-119 [doi]
- An Extensible Evaluation Platform for FPGA Bitstream Obfuscation SecurityShakil Mahmud, Brooks Olney, Robert Karam. 120-125 [doi]
- Lorax: Machine Learning-Based Oracle Reconstruction With Minimal I/O PatternsWei Zeng 0015, Azadeh Davoodi, Rasit Onur Topaloglu. 126-131 [doi]
- Towards Enhancing Power-Analysis Attack Resilience for Logic Locking TechniquesZhiming Zhang, Ivan Miketic, Emre Salman, Qiaoyan Yu. 132-137 [doi]
- Heartbeat Classification with Spiking Neural Networks on the Loihi Neuromorphic ProcessorKyle Buettner, Alan D. George. 138-143 [doi]
- A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGATongtong Yin, Wendong Mao, Jinming Lu, Zhongfeng Wang. 144-149 [doi]
- Analog Circuit Implementation of Neural Networks for In-Sensor ComputingJianghan Zhu, Bingzhen Chen, Zhitao Yang, Lingxiao Meng, Terry Tao Ye. 150-156 [doi]
- Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory CyclesJohn Reuben, Dietmar Fey. 157-163 [doi]
- A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNsFlavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza. 164-169 [doi]
- FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative MethodNoureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory. 170-175 [doi]
- SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETsSachin Bhat, Mingyu Li, Sounak Shaun Ghosh, Sourabh Kulkarni, Csaba Andras Moritz. 176-181 [doi]
- PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGALuyi Li, Jun Lin, Zhongfeng Wang. 182-187 [doi]
- An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile DevicesMohammed Elbtity, Abhishek Singh, Brendan Reidy, Xiaochen Guo, Ramtin Zand. 188-193 [doi]
- Dynamic Fault Tree Models for FPGA Fault Tolerance and ReliabilityYassmeen Elderhalli, Nahla El-Araby, Osman Hasan, Axel Jantsch, Sofiène Tahar. 194-199 [doi]
- ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN ProcessingSupreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi. 200-205 [doi]
- n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM AcceleratorMahboobe Sadeghipour Roodsari, Hanieh Totonchi Asl, Zainalabedin Navabi. 206-211 [doi]
- Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain SupportQilin Si, Imtiaz Rashid, Benjamin Carrión Schäfer. 212-217 [doi]
- Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point ArithmeticYuk Wong, Zhenjiang Dong, Wei Zhang. 218-223 [doi]
- Custom enhancements to networked processor templatesTim Todman, Wayne Luk. 224-229 [doi]
- Analyzing the Design Space of Spatial Tensor Accelerators on FPGAsLiancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang 0001. 230-235 [doi]
- Side-channel Leakage Assessment Metrics: A Case Study of GIFT Block CiphersWilliam Unger, Liljana Babinkostova, Mike Borowczak, Robert Erbes. 236-241 [doi]
- Stealing Machine Learning Parameters via Side Channel Power AttacksShaya Wolf, Hui Hu, Rafer Cooley, Mike Borowczak. 242-247 [doi]
- Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-ChipSubashree Raja, Padmaja Bhamidipati, Xiaobang Liu, Ranga Vemuri. 248-253 [doi]
- An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN TrainingHaikuo Shao, Jinming Lu, Jun Lin, Zhongfeng Wang. 254-259 [doi]
- Accelerating Spectral Normalization for Enhancing Robustness of Deep Neural NetworksZhixin Pan, Prabhat Mishra 0001. 260-265 [doi]
- A Microarchitecture Implementation Framework for Online Learning with Temporal Neural NetworksHarideep Nair, John Paul Shen, James E. Smith. 266-271 [doi]
- Neural Networks as a Side-Channel Countermeasure: Challenges and OpportunitiesJonas Krautter, Mehdi B. Tahoori. 272-277 [doi]
- New Security Threats on FPGAs: From FPGA Design Tools PerspectiveSandeep Sunkavilli, Zhiming Zhang, Qiaoyan Yu. 278-283 [doi]
- A Survey of Recent Attacks and Mitigation on FPGA SystemsShijin Duan, Wenhao Wang, Yukui Luo, Xiaolin Xu. 284-289 [doi]
- A Security Architecture for Domain Isolation in Multi-Tenant Cloud FPGAsJoel Mandebi Mbongue, Sujan Kumar Saha, Christophe Bobda. 290-295 [doi]
- Efficient Hardware Implementation of PQC Primitives and PQC algorithms Using High-Level SynthesisDeepraj Soni, Ramesh Karri. 296-301 [doi]
- th Power and Root ComputationAdrian Tatulian, Ronald F. DeMara. 302-307 [doi]
- Design of An Approximate FFT Processor Based on Approximate Complex MultipliersJinhe Du, Ke Chen 0018, Peipei Yin, Chenggang Yan, Weiqiang Liu. 308-313 [doi]
- Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT DevicesZachary Kahleifeh, Himanshu Thapliyal. 314-319 [doi]
- Proposal of A Novel Hybrid NAND-Like MRAM/DRAM Memory ArchitectureKuiqing He, Zhi Yang, Zhitai Yu, Jianglong Zhi, Zhaohao Wang, Yijiao Wang. 320-325 [doi]
- Oscillatory Neural Networks for Edge AI ComputingCorentin Delacour, Stefania Carapezzi, Madeleine Abernot, Gabriele Boschetto, Nadine Azémard, Jérémie Salles, Thierry Gil, Aida Todri-Sanial. 326-331 [doi]
- EQUAL: Efficient QUasi Adiabatic Logic for Enhanced Side-Channel ResistanceKrithika Dhananjay, Emre Salman. 332-337 [doi]
- Scalable Resonant Power Clock Generation for Adiabatic Logic DesignRagh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin. 338-342 [doi]
- HEXON: Protecting Firmware Using Hardware-Assisted Execution-Level ObfuscationMuhammad Monir Hossain, Sajeed Mohammad, Jason Vosatka, Jeffery S. Allen, Monica Allen, Farimah Farahmandi, Fahim Rahman, Mark Mohammad Tehranipoor. 343-349 [doi]
- Enhancing PRESENT-80 and Substitution-Permutation Network Cipher Security with Dynamic "Keyed" Permutation NetworksMatthew Lewandowski, Srinivas Katkoori. 350-355 [doi]
- Countering PUF Modeling Attacks through Adversarial Machine LearningMohammad Ebrahimabadi, Wassila Lalouani, Mohamed F. Younis, Naghmeh Karimi. 356-361 [doi]
- LightRoAD: Lightweight Rowhammer Attack DetectorMottaqiallah Taouil, Cezar Reinbrecht, Said Hamdioui, Johanna Sepúlveda. 362-367 [doi]
- Minimized Region of Path-search Algorithm for ASIP-based Connection Allocator in NoCsSeungseok Nam, Emil Matús, Gerhard P. Fettweis. 368-373 [doi]
- Improved Polygon Method for HIL Simulations in Real TimeMarina Yushkova, Alberto Sanchez, Angel de Castro. 374-377 [doi]
- Machine Learning for VLSI CAD: A Case Study in On-Chip Power Grid DesignSukanta Dey, Sukumar Nandi, Gaurav Trivedi. 378-383 [doi]
- MCTS-based Synthesis Towards Efficient Approximate AcceleratorsMuhammad Awais 0009, Marco Platzner. 384-389 [doi]
- Wearable Health Monitoring System for Older Adults in a Smart Home EnvironmentRajdeep Kumar Nath, Himanshu Thapliyal. 390-395 [doi]
- Implementation of a QPSK Symbol Synchronizer in Xilinx System GeneratorBradley Comar. 396-401 [doi]
- Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate BlocksMohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun. 402-405 [doi]
- A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural NetworksSajjad Parvin, Mustafa Altun. 406-411 [doi]
- Hardware Trojan Classification at Gate-level Netlists based on Area and Power Machine Learning AnalysisKonstantinos G. Liakos, Georgios K. Georgakilas, Fotis C. Plessas. 412-417 [doi]
- FPGA Implementation of High Speed Anti-notch Lattice filter for Exon Region Identification in Eukaryotic GenesVikas Pathak, Satyasai Jagannath Nanda, Amit Mahesh Joshi, Sitanshu Sekhar Sahu. 418-421 [doi]
- A Quantum Variational Approach to Debugging Combinational Logic CircuitsPeter Demetriou, Conrad J. Haupt, Ken J. Nixon. 422-427 [doi]
- Analyzing crosstalk error in the NISQ eraSiyuan Niu, Aida Todri-Sanial. 428-430 [doi]
- Automated Flag Qubit Insertion for Reliable Quantum Circuit OutputNikita Acharya, Samah Mohamed Saeed. 431-436 [doi]
- Fast quantum circuit simulation using hardware accelerated general purpose librariesOumarou Oumarou, Alexandru Paler, Robert Basmadjian. 437-440 [doi]
- Implementation of Grover's Algorithm to Solve the Maximum Clique ProblemA. Haverly, S. López. 441-446 [doi]
- Importance of Diagonal Gates in Tensor Network SimulationsDanylo Lykov, Yuri Alexeev. 447-452 [doi]
- Quantum Annealing for Automated Feature Selection in Stress DetectionRajdeep Kumar Nath, Himanshu Thapliyal, Travis S. Humble. 453-457 [doi]
- Reproducibility in Quantum ComputingSamudra Dasgupta, Travis S. Humble. 458-461 [doi]
- Towards Automated Superconducting Circuit Calibration using Deep Reinforcement LearningMeriam Gay Bautista, Zhi Jackie Yao, Anastasiia Butko, Mariam Kiran, Mekena Metcalf. 462-467 [doi]