Ming Ming Wong, Vikramkumar Pudi, Anupam Chattopadhyay. Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor. In IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018. pages 95-100, IEEE, 2018. [doi]
@inproceedings{WongPC18,
title = {Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor},
author = {Ming Ming Wong and Vikramkumar Pudi and Anupam Chattopadhyay},
year = {2018},
doi = {10.1109/VLSI-SoC.2018.8644825},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644825},
researchr = {https://researchr.org/publication/WongPC18},
cites = {0},
citedby = {0},
pages = {95-100},
booktitle = {IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
publisher = {IEEE},
isbn = {978-1-5386-4756-1},
}