Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie

Derek Wright, Manoj Sachdev. Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie. In Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA. pages 39-47, IEEE Computer Society, 2003. [doi]

@inproceedings{WrightS03:0,
  title = {Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie},
  author = {Derek Wright and Manoj Sachdev},
  year = {2003},
  url = {http://csdl.computer.org/comp/proceedings/itc/2003/2063/00/20630039abs.htm},
  tags = {testing, analysis},
  researchr = {https://researchr.org/publication/WrightS03%3A0},
  cites = {0},
  citedby = {0},
  pages = {39-47},
  booktitle = {Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA},
  publisher = {IEEE Computer Society},
  isbn = {0-7803-8106-8},
}