Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes

Meng-Yen Wu, Meng-Hsueh Chiang. Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes. In 17th International Symposium on Quality Electronic Design, ISQED 2016, Santa Clara, CA, USA, March 15-16, 2016. pages 169-172, IEEE, 2016. [doi]

@inproceedings{WuC16-10,
  title = {Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes},
  author = {Meng-Yen Wu and Meng-Hsueh Chiang},
  year = {2016},
  doi = {10.1109/ISQED.2016.7479195},
  url = {http://dx.doi.org/10.1109/ISQED.2016.7479195},
  researchr = {https://researchr.org/publication/WuC16-10},
  cites = {0},
  citedby = {0},
  pages = {169-172},
  booktitle = {17th International Symposium on Quality Electronic Design, ISQED 2016, Santa Clara, CA, USA, March 15-16, 2016},
  publisher = {IEEE},
  isbn = {978-1-5090-1213-8},
}