Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications

Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang. Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. In 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015. pages 339-344, IEEE, 2015. [doi]

@inproceedings{WuCCHSC15,
  title = {Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications},
  author = {Tse-Ching Wu and Chien-Ju Chen and Yin-Nien Chen and Vita Pi-Ho Hu and Pin Su and Ching-Te Chuang},
  year = {2015},
  doi = {10.1109/SOCC.2015.7406978},
  url = {http://dx.doi.org/10.1109/SOCC.2015.7406978},
  researchr = {https://researchr.org/publication/WuCCHSC15},
  cites = {0},
  citedby = {0},
  pages = {339-344},
  booktitle = {28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015},
  publisher = {IEEE},
  isbn = {978-1-4673-9094-1},
}